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    SYSTEMS AND TECHNIQUES FOR ACCESSING MULTIPLE MEMORY CELLS CONCURRENTLY
    1.
    发明公开
    SYSTEMS AND TECHNIQUES FOR ACCESSING MULTIPLE MEMORY CELLS CONCURRENTLY 审中-公开

    公开(公告)号：US20240013833A1

    公开(公告)日：2024-01-11

    申请号：US18208103

    申请日：2023-06-09

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0061 ,  G11C13/004 ,  G11C2013/0045

    Abstract: Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

    Semiconductor packages with patterns of die-specific information
    2.
    发明授权
    Semiconductor packages with patterns of die-specific information 有权

    公开(公告)号：US11031258B2

    公开(公告)日：2021-06-08

    申请号：US16548126

    申请日：2019-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: H01L23/02 ,  H01L21/56 ,  H01L21/78 ,  H01L23/28 ,  H01L23/00

    Abstract: Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner.

    SEMICONDUCTOR PACKAGES WITH INDICATIONS OF DIE-SPECIFIC INFORMATION
    3.
    发明申请
    SEMICONDUCTOR PACKAGES WITH INDICATIONS OF DIE-SPECIFIC INFORMATION 有权

    公开(公告)号：US20210057232A1

    公开(公告)日：2021-02-25

    申请号：US16548084

    申请日：2019-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/28 ,  H01L23/00

    Abstract: Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) an indication positioned in a designated area of the first surface. The indication includes a code presenting information for operating the semiconductor die. The code is configured to be read by an indication scanner coupled to a controller.

    METHOD OF DYNAMICALLY SELECTING MEMORY CELL CAPACITY
    5.
    发明申请
    METHOD OF DYNAMICALLY SELECTING MEMORY CELL CAPACITY 有权
    动态选择存储单元容量的方法

    公开(公告)号：US20150262628A1

    公开(公告)日：2015-09-17

    申请号：US14728900

    申请日：2015-06-02

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: G11C5/14 ,  G11C14/00 ,  G11C16/10 ,  G11C7/10 ,  G06F12/02

    CPC classification number: G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

    Abstract: Subject matter disclosed herein relates to techniques to use a memory device. A method includes receiving a memory instruction comprising at least one parameter representative of at least one threshold voltage value and a read command to read at least one cell of the memory device. The method further includes detecting at least one voltage value from the at least one cell. The method further includes comparing the at least one voltage value to the at least one threshold voltage value. The method further includes determining at least one logical value of the at least one cell in response to the comparison of the at least one voltage value to the at least one threshold voltage value.

    Abstract translation: 本文公开的主题涉及使用存储器件的技术。 一种方法包括接收包含至少一个表示至少一个阈值电压值的参数和读取命令的存储器指令以读取存储器件的至少一个单元。 该方法还包括从至少一个小区检测至少一个电压值。 该方法还包括将至少一个电压值与至少一个阈值电压值进行比较。 所述方法还包括响应于所述至少一个电压值与所述至少一个阈值电压值的比较来确定所述至少一个单元的至少一个逻辑值。

    THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE
    6.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE 有权
    三维存储阵列架构

    公开(公告)号：US20150044849A1

    公开(公告)日：2015-02-12

    申请号：US14470247

    申请日：2014-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

    Abstract translation: 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部，使得 至少一个导电延伸部与多个第一导线中的至少一个的一部分相交。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。

    THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE
    7.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE 有权
    三维存储阵列架构

    公开(公告)号：US20140295638A1

    公开(公告)日：2014-10-02

    申请号：US14268649

    申请日：2014-05-02

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/249 ,  H01L29/41758 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    Abstract: Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.

    Abstract translation: 提供三维存储器阵列结构及其形成方法。 示例性存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个级别的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。 所述至少一个导电延伸部，存储元件材料和电池选择材料位于所述多个第一导电线的共面对之间。

    Systems and techniques for accessing multiple memory cells concurrently
    9.
    发明授权
    Systems and techniques for accessing multiple memory cells concurrently 有权

    公开(公告)号：US12249370B2

    公开(公告)日：2025-03-11

    申请号：US18208103

    申请日：2023-06-09

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: G11C13/00

    Abstract: Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

    Redundant cloud memory storage for a memory subsystem
    10.
    发明授权
    Redundant cloud memory storage for a memory subsystem 有权

    公开(公告)号：US11360868B2

    公开(公告)日：2022-06-14

    申请号：US16434602

    申请日：2019-06-07

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G06F3/06

    Abstract: A method for managing memory element failures in a memory subsystem is described. The method includes detecting, by the memory subsystem, a failed memory element in the memory subsystem and transmitting a redundant memory request based on detection of the failed memory element. The redundant memory request seeks to utilize memory storage in an external storage system in place of the failed memory element in the memory subsystem. Thereafter, the memory subsystem receives, from the external storage system, a redundant memory request confirmation, which indicates that the redundant memory request has been fulfilled and includes an address of a location in the external storage system. In response to receipt of the redundant memory request confirmation, the memory subsystem updates memory management information to map a logical address, which was previously mapped to the failed memory element, to the location in the external storage system.

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