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    SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING CONDUCTIVE LINES AND PERIPHERAL CONDUCTIVE PADS
    3.
    发明申请
    SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING CONDUCTIVE LINES AND PERIPHERAL CONDUCTIVE PADS 有权
    半导体结构和器件，包括导电线和外围导电垫

    公开(公告)号：US20150280116A1

    公开(公告)日：2015-10-01

    申请号：US14739452

    申请日：2015-06-15

    Applicant: Micron Technology, Inc.

    Inventor： Giulio Albini

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L21/7684 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

    Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

    Abstract translation: 诸如相变存储器件的半导体器件和结构包括耦合到外围区域中的外围导电触点的外围导电焊盘。 阵列区域可以包括耦合到导线的存储单元。 形成这样的半导体器件和结构的方法包括从周边区域去除存储单元材料，然后从阵列区域选择性地去除存储单元材料的部分，以限定阵列区域中的各个存储单元。 附加的方法包括使用外围导电焊盘和/或间隔物材料在外围导电焊盘上平坦化结构作为平坦化停止材料。 另外的方法包括部分地限定阵列区域中的存储器单元，之后形成外围导电触点，然后完全限定存储单元。

    Low resistance via contacts in a memory device
    5.
    发明授权
    Low resistance via contacts in a memory device 有权

    公开(公告)号：US12193341B2

    公开(公告)日：2025-01-07

    申请号：US17875691

    申请日：2022-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Giulio Albini

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.

    METHODS OF FORMING SEMICONDUCTOR DEVICES AND STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RESULTING STRUCTURES AND SEMICONDUCTOR DEVICES
    8.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES AND STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RESULTING STRUCTURES AND SEMICONDUCTOR DEVICES 有权
    形成具有改进的平面化均匀性的半导体器件和结构的方法，以及结构和半导体器件

    公开(公告)号：US20150083986A1

    公开(公告)日：2015-03-26

    申请号：US14038164

    申请日：2013-09-26

    Applicant: Micron Technology, Inc.

    Inventor： Giulio Albini

    IPC: H01L45/00

    CPC classification number: H01L21/7684 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

    Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

    Abstract translation: 诸如相变存储器件的半导体器件和结构包括耦合到外围区域中的外围导电触点的外围导电焊盘。 阵列区域可以包括耦合到导线的存储单元。 形成这样的半导体器件和结构的方法包括从周边区域去除存储单元材料，然后从阵列区域选择性地去除存储单元材料的部分，以限定阵列区域中的各个存储单元。 附加的方法包括使用外围导电焊盘和/或间隔物材料在外围导电焊盘上平坦化结构作为平坦化停止材料。 另外的方法包括部分地限定阵列区域中的存储器单元，之后形成外围导电触点，然后完全限定存储单元。

    LOW RESISTANCE VIA CONTACTS IN A MEMORY DEVICE
    10.
    发明申请
    LOW RESISTANCE VIA CONTACTS IN A MEMORY DEVICE 有权

    公开(公告)号：US20250107459A1

    公开(公告)日：2025-03-27

    申请号：US18972316

    申请日：2024-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Giulio Albini

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.

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