公开(公告)号：US20250166245A1

公开(公告)日：2025-05-22

申请号：US18952510

申请日：2024-11-19

Applicant: Micron Technology, Inc.

Inventor： Mohad Baboli ,  John Hopkins

IPC: G06T11/00 ,  H04N23/13

Abstract: A system and method for providing multispectral vision using a transmitting device or a receiving device with integrated sensors. The transmitting device captures and distributes multispectral information. A receiving device processes non-visible data into enhanced visual representations presented to the user. Alternatively, the receiving device translates non-visible data into neuronal maps transmitted to a linked neuronal interface worn by the user. The interface stimulates the visual cortex with electrical impulses inducing perception of the multispectral information. The flexible architectures enable sensing beyond normal human vision limits by converting non-visible data through visual representation or direct neural stimulation.

公开(公告)号：US20250066910A1

公开(公告)日：2025-02-27

申请号：US18773920

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Jordan D. Greenlee

IPC: H01J37/32 ,  C23C16/44

Abstract: A semiconductor manufacture reclamation system and associated methods are shows. Example systems and methods include semiconductor processing machinery and a reaction chamber coupled along a path of a waste gas vent. Systems and methods are shown that include an amount of silicon to react with a waste gas including tungsten.

公开(公告)号：US12218008B2

公开(公告)日：2025-02-04

申请号：US18200852

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.

公开(公告)号：US20230397419A1

公开(公告)日：2023-12-07

申请号：US17816651

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Wesley O. Mckinsey ,  John Hopkins

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556

Abstract: For manufacturing a memory device, a system may form a trench between a first portion and a second portion of a stack. A bottom wall of the trench may include a spacer material. The system may remove a first and a second oxide material to reform the trench, and remove a polysilicon material in a lateral direction to expose a third oxide material and a channel structure. The third oxide material may form the bottom wall of the trench. The system may remove, in a lateral direction, the first oxide material, a portion of the second oxide material, the third oxide material, and a fourth oxide material of the channel structure. The system may deposit a metal material, in the trench, in contact with a doped polysilicon material of the channel structure.

公开(公告)号：US11626424B2

公开(公告)日：2023-04-11

申请号：US17397338

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11563

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20220310525A1

公开(公告)日：2022-09-29

申请号：US17216264

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett Allen McTeer ,  John Hopkins

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separated from the first dielectric material; a memory cell string including a pillar extending through the first and second dielectric materials, the pillar including a portion between the first and second dielectric materials; and a tungsten material located between the first and second dielectric materials and separated from the portion of the pillar and the first and second dielectric materials by an additional dielectric material. The additional dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide. The additional dielectric material contacts the portion of the pillar and the tungsten material.

公开(公告)号：US20200266280A1

公开(公告)日：2020-08-20

申请号：US16799517

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan

IPC: H01L29/49 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11556

Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

公开(公告)号：US20180315766A1

公开(公告)日：2018-11-01

申请号：US16028111

申请日：2018-07-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/285 ,  H01L21/311 ,  H01L29/51 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/513 ,  H01L29/66825

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US09793282B2

公开(公告)日：2017-10-17

申请号：US14925589

申请日：2015-10-28

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US20160284728A1

公开(公告)日：2016-09-29

申请号：US15174478

申请日：2016-06-06

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/115 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有多层存储器单元和相关控制门的装置和方法。 一种方法包括形成具有交替的导体材料和电介质材料的第一甲板和包含延伸穿过导体材料和电介质材料的材料的孔。 所述方法还可以包括在所述孔的扩大部分中形成牺牲材料并在所述第一甲板上形成第二层记忆单元。 描述附加的装置和方法。