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公开(公告)号：US10658034B1
公开(公告)日：2020-05-19
申请号：US16182101
申请日：2018-11-06
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra , Paolo Amato
Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.
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公开(公告)号：US20190189206A1
公开(公告)日：2019-06-20
申请号：US15842504
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C2013/0052 , G11C2013/0092 , G11C2213/30 , G11C2213/71 , H01L27/2463 , H01L45/1253 , H01L45/141
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US11942183B2
公开(公告)日：2024-03-26
申请号：US17502481
申请日：2021-10-15
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Richard K. Dodge , Innocenzo Tortorelli , Mattia Robustelli , Mario Allegra
CPC classification number: G11C7/1096 , G11C7/1051
Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).
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公开(公告)号：US20210272615A1
公开(公告)日：2021-09-02
申请号：US17325997
申请日：2021-05-20
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra
IPC: G11C11/16
Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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公开(公告)号：US20200279604A1
公开(公告)日：2020-09-03
申请号：US16876641
申请日：2020-05-18
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra , Paolo Amato
Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.
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Patent Agency Ranking
公开(公告)号：US20190244665A1
公开(公告)日：2019-08-08
申请号：US16387234
申请日：2019-04-17
Applicant: Micron Technology, Inc.
Inventor： Mario Allegra , Mattia Boniardi
CPC classification number: G11C13/0069 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C2013/009 , H01L27/2409 , H01L27/2427 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1675
Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.
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公开(公告)号：US20240203468A1
公开(公告)日：2024-06-20
申请号：US18593635
申请日：2024-03-01
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Richard K. Dodge , Innocenzo Tortorelli , Mattia Robustelli , Mario Allegra
IPC: G11C7/10
CPC classification number: G11C7/1096 , G11C7/1051
Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).
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公开(公告)号：US20220115068A1
公开(公告)日：2022-04-14
申请号：US17499290
申请日：2021-10-12
Applicant: Micron Technology, Inc
Inventor： Innocenzo Tortorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20220108732A1
公开(公告)日：2022-04-07
申请号：US17502481
申请日：2021-10-15
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Richard K. Dodge , Innocenzo Tortorelli , Mattia Robustelli , Mario Allegra
IPC: G11C7/10
Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).
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公开(公告)号：US11114159B2
公开(公告)日：2021-09-07
申请号：US16876641
申请日：2020-05-18
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra , Paolo Amato
Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.
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