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公开(公告)号:US11961556B2
公开(公告)日:2024-04-16
申请号:US17568461
申请日:2022-01-04
IPC分类号: G11C5/06 , G11C13/00 , H01L23/522 , H01L23/528 , H10B63/00 , H10N70/00 , H10N70/20
CPC分类号: G11C13/0028 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , H01L23/5226 , H01L23/528 , H10B63/84 , H10N70/231 , H10N70/826 , G11C2213/52 , G11C2213/71 , H10N70/841 , H10N70/8825
摘要: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.
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2.
公开(公告)号:US20230343393A1
公开(公告)日:2023-10-26
申请号:US17727487
申请日:2022-04-22
IPC分类号: G11C16/04 , H01L23/48 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582
CPC分类号: G11C16/0483 , H01L23/481 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582
摘要: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier that comprises silicon-containing material. The stack comprises laterally-spaced memory-block regions and a through-array-via (TAV) region. The stack comprises channel-material strings that extend through the first tiers and the second tiers in the memory-block regions. The stack comprises TAV openings in the TAV region that extend to the silicon-containing material of the conductor tier. A metal halide is reacted with the silicon of the silicon-containing material to deposit the metal of the metal halide in the conductor tier. After depositing the metal, conductive material is formed in the TAV openings directly against the deposited metal and therefrom a TAV is formed in individual of the TAV openings that comprises the conductive material and the deposited metal. Structure embodiments are disclosed.
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3.
公开(公告)号:US20230207469A1
公开(公告)日:2023-06-29
申请号:US17582280
申请日:2022-01-24
IPC分类号: H01L23/535 , H01L27/11556 , H01L27/11582
CPC分类号: H01L23/535 , H01L27/11556 , H01L27/11582
摘要: A memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAV constructions comprise an upper portion directly above and joined with a lower portion. The individual TAV constructions comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method, are disclosed.
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公开(公告)号:US11380732B2
公开(公告)日:2022-07-05
申请号:US16941885
申请日:2020-07-29
发明人: Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
摘要: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
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公开(公告)号:US20220208264A1
公开(公告)日:2022-06-30
申请号:US17568461
申请日:2022-01-04
IPC分类号: G11C13/00 , H01L23/528 , H01L23/522 , H01L27/24 , H01L45/00
摘要: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.
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公开(公告)号:US20220037403A1
公开(公告)日:2022-02-03
申请号:US16941885
申请日:2020-07-29
发明人: Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
摘要: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
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7.
公开(公告)号:US20230395150A1
公开(公告)日:2023-12-07
申请号:US18327846
申请日:2023-06-01
发明人: Rui Zhang , Shuangqiang Luo , Mohad Baboli , Rajasekhar Venigalla
IPC分类号: G11C16/04 , H10B41/35 , H10B41/27 , H10B43/27 , H10B43/35 , H01L23/522 , H01L23/528 , H01L21/768
CPC分类号: G11C16/0483 , H10B41/35 , H10B41/27 , H10B43/27 , H10B43/35 , H01L23/5226 , H01L23/5283 , H01L21/76831
摘要: A microelectronic device includes a stack structure including blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The blocks including a stadium structure including opposing staircase structures each having steps comprising edges of the tiers. The blocks further include a filled trench vertically overlying and within horizontal boundaries of the stadium structure. The filled trench includes dielectric liner structures and additional dielectric liner structures having a different material composition than that of the dielectric liner structures and alternating with the dielectric liner structures. The filled trench also includes dielectric fill material overlying an alternating sequence of the dielectric liner structures and additional dielectric liner structures.
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公开(公告)号:US20240224825A1
公开(公告)日:2024-07-04
申请号:US18409413
申请日:2024-01-10
发明人: Rajasekhar Venigalla , Patrick M. Flynn , Josiah Jebaraj Johnley Muthuraj , Efe Sinan Ege , Kevin Lee Baker , Tao Nguyen , Davis Weymann
IPC分类号: H10N70/00 , G11C13/00 , H01L21/768 , H01L23/522 , H01L23/528 , H10B63/00 , H10N70/20
CPC分类号: H10N70/8616 , G11C13/0004 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/528 , H10B63/84 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/841 , G11C13/004 , G11C2013/005 , G11C13/0069 , G11C2013/0078 , G11C2213/52 , G11C2213/71 , H10N70/8825
摘要: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
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公开(公告)号:US11882774B2
公开(公告)日:2024-01-23
申请号:US17468167
申请日:2021-09-07
发明人: Rajasekhar Venigalla , Patrick M. Flynn , Josiah Jebaraj Johnley Muthuraj , Efe Sinan Ege , Kevin Lee Baker , Tao Nguyen , Davis Weymann
IPC分类号: H10N70/00 , H01L21/768 , H01L23/522 , G11C13/00 , H01L23/528 , H10B63/00 , H10N70/20
CPC分类号: H10N70/8616 , G11C13/0004 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/528 , H01L23/5226 , H10B63/84 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/841 , G11C13/004 , G11C13/0069 , G11C2013/005 , G11C2013/0078 , G11C2213/52 , G11C2213/71 , H10N70/8825
摘要: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
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公开(公告)号:US20220406847A1
公开(公告)日:2022-12-22
申请号:US17846731
申请日:2022-06-22
发明人: Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
摘要: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
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