Memory with optimized resistive layers

    公开(公告)号:US11380732B2

    公开(公告)日:2022-07-05

    申请号:US16941885

    申请日:2020-07-29

    IPC分类号: H01L27/24 H01L45/00

    摘要: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

    SOCKET DESIGN FOR A MEMORY DEVICE

    公开(公告)号:US20220208264A1

    公开(公告)日:2022-06-30

    申请号:US17568461

    申请日:2022-01-04

    摘要: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

    MEMORY WITH OPTIMIZED RESISTIVE LAYERS

    公开(公告)号:US20220037403A1

    公开(公告)日:2022-02-03

    申请号:US16941885

    申请日:2020-07-29

    IPC分类号: H01L27/24 H01L45/00

    摘要: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

    MEMORY WITH OPTIMIZED RESISTIVE LAYERS

    公开(公告)号:US20220406847A1

    公开(公告)日:2022-12-22

    申请号:US17846731

    申请日:2022-06-22

    IPC分类号: H01L27/24 H01L45/00

    摘要: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.