公开(公告)号：US11848048B2

公开(公告)日：2023-12-19

申请号：US17456968

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Chandra S. Danana ,  Durga P. Panda ,  Luca Laurin ,  Michael J. Irwin ,  Rekha Chithra Thomas ,  Sara Vigano ,  Stephen W. Russell ,  Zia A. Shafi

IPC: G11C11/00 ,  G11C13/00 ,  H01L29/423 ,  H10B63/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H01L29/4236 ,  H01L29/42376 ,  H10B63/84 ,  G11C2213/71

Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.

公开(公告)号：US10153194B2

公开(公告)日：2018-12-11

申请号：US15584413

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Marcello D. Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/744 ,  H01L21/308 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/102 ,  H01L21/8229 ,  H01L27/105 ,  H01L29/423 ,  H01L29/749

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US09673054B2

公开(公告)日：2017-06-06

申请号：US14461751

申请日：2014-08-18

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L21/8249 ,  H01L21/308 ,  H01L29/78 ,  H01L29/744 ,  H01L27/102

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/8229 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/8239 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/1027 ,  H01L27/1052 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/744 ,  H01L29/749 ,  H01L29/7827

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US10923387B2

公开(公告)日：2021-02-16

申请号：US16577012

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L27/11551 ,  H01L21/762 ,  H01L29/78 ,  H01L29/744 ,  H01L21/308 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/102 ,  H01L29/749 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/423

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US10460981B2

公开(公告)日：2019-10-29

申请号：US16183493

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L27/11551 ,  H01L21/762 ,  H01L29/78 ,  H01L29/744 ,  H01L21/308 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/102 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/423 ,  H01L29/749

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US09646875B2

公开(公告)日：2017-05-09

申请号：US14931152

申请日：2015-11-03

Applicant: Micron Technology, Inc.

Inventor： Niccolo Righetti ,  Sara Vigano ,  Emelio Camerlenghi

IPC: H01L21/76 ,  H01L21/768 ,  H01L27/06 ,  H01L27/105

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

公开(公告)号：US20190088534A1

公开(公告)日：2019-03-21

申请号：US16183493

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L21/762 ,  H01L21/308 ,  H01L29/749 ,  H01L29/744 ,  H01L21/8249 ,  H01L21/8239 ,  H01L29/66 ,  H01L27/102 ,  H01L27/105 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/8229 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/8229 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/8239 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/1027 ,  H01L27/1052 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/744 ,  H01L29/749 ,  H01L29/7827

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US09214389B2

公开(公告)日：2015-12-15

申请号：US14265168

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Niccolo′ Righetti ,  Sara Vigano ,  Emilio Camerlenghi

IPC: H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 形成了在较低水平上具有较高水平的组件。 下层包括电路。 上层包括存储器阵列区域内的半导体材料，并且在存储器阵列区域周围的区域中包括绝缘材料。 第一和第二沟槽形成为延伸到半导体材料中。 第一和第二沟槽将半导体材料图案化成多个基座。 第二沟槽延伸到周边区域。 在周边区域内形成接触开口以从第二沟槽延伸到电路的第一级。 导电材料形成在第二沟槽内部和接触开口内。 导电材料在第二沟槽内形成感测/接入线，并在接触开口内形成电接触，以将感测/接入线电耦合到较低级别的电路。

公开(公告)号：US20150311115A1

公开(公告)日：2015-10-29

申请号：US14265168

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Niccolo' Righetti ,  Sara Vigano ,  Emilio Camerlenghi

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 形成了在较低水平上具有较高水平的组件。 下层包括电路。 上层包括存储器阵列区域内的半导体材料，并且在存储器阵列区域周围的区域中包括绝缘材料。 第一和第二沟槽形成为延伸到半导体材料中。 第一和第二沟槽将半导体材料图案化成多个基座。 第二沟槽延伸到周边区域。 在周边区域内形成接触开口以从第二沟槽延伸到电路的第一级。 导电材料形成在第二沟槽内部和接触开口内。 导电材料在第二沟槽内形成感测/接入线，并在接触开口内形成电接触，以将感测/接入线电耦合到较低级别的电路。

公开(公告)号：US20230170015A1

公开(公告)日：2023-06-01

申请号：US17456968

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Chandra S. Danana ,  Durga P. Panda ,  Luca Laurin ,  Michael J. Irwin ,  Rekha Chithra Thomas ,  Sara Vigano ,  Stephen W. Russell ,  Zia A. Shafi

IPC: G11C13/00 ,  H01L27/24 ,  H01L29/423

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H01L27/2481 ,  H01L29/4236 ,  H01L29/42376 ,  G11C2213/71

Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.