公开(公告)号：US11829612B2

公开(公告)日：2023-11-28

申请号：US17396528

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Lance W Dover ,  Steffen Buch

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for security techniques for low power state of memory device are described. A host device may initiate a low power state of a memory device. The host device may store a first value of a counter associated with the memory device operating in the low power state and transmit a command to the memory device to enter the low power state. The memory device may increment the counter based on receiving the command and increment the counter to a second value. The host device may validate the memory device based on a difference between the first value of the counter stored by the host device and the second value of the counter.

公开(公告)号：US20220179733A1

公开(公告)日：2022-06-09

申请号：US17529925

申请日：2021-11-18

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods, systems, and devices for error type indication are described. A memory device may detect an error while performing an error detection procedure for a codeword. The memory device may transmit to a host device one or more bits, which may be one or more error flags, that indicate the type of error detected by the memory device. By transmitting the one or more bits to a requesting device, for example a host device, the memory device may indicate the detected presence of a particular type of error in the set of data that is returned to the requesting device.

公开(公告)号：US20220057945A1

公开(公告)日：2022-02-24

申请号：US17396528

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Lance W. Dover ,  Steffen Buch

IPC: G06F3/06

Abstract: Methods, systems, and devices for security techniques for low power state of memory device are described. A host device may initiate a low power state of a memory device. The host device may store a first value of a counter associated with the memory device operating in the low power state and transmit a command to the memory device to enter the low power state. The memory device may increment the counter based on receiving the command and increment the counter to a second value. The host device may validate the memory device based on a difference between the first value of the counter stored by the host device and the second value of the counter.

公开(公告)号：US12242343B2

公开(公告)日：2025-03-04

申请号：US18049454

申请日：2022-10-25

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe ,  Aaron P. Boehm ,  Scott E. Schaefer ,  Steffen Buch

IPC: G06F11/10 ,  G06F11/07

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

公开(公告)号：US12189832B2

公开(公告)日：2025-01-07

申请号：US17396531

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Lance W. Dover ,  Steffen Buch

IPC: G06F21/79 ,  G06F21/60 ,  H04L9/06 ,  H04L9/08 ,  H04L9/32 ,  G06F21/64 ,  G06F21/72 ,  G06F21/78

Abstract: Data associated with a memory device may be authenticated before an associated operation is executed. The data may be authenticated before it is executed at a volatile memory. The data may be associated with a hash (e.g., a first hash) and may be communicated from the memory device to a host device. At the host device, the data and the first hash may be written (e.g., stored) to temporary storage, such as a cache. Once stored to the cache, the host device may generate an additional hash (e.g., a second hash) related to the data using a key inaccessible to the memory device. If the first hash and second hash match, the data may be authenticated and one or more operations may be executed.

公开(公告)号：US12001707B2

公开(公告)日：2024-06-04

申请号：US17396529

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Steffen Buch ,  Lance W. Dover

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0623 ,  G06F3/0679

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

公开(公告)号：US11934267B1

公开(公告)日：2024-03-19

申请号：US17897186

申请日：2022-08-28

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/0763 ,  G06F11/0772

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with a data inversion and unidirectional error detection are described. An apparatus for data inversion and unidirectional error detection can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to encode a plurality of binary data bits in an information word, encode the information word using a unidirectional error detecting code, write the encoded information word to the memory device, read the encoded information word from the memory device, and detect an error in the information word using a unidirectional error detecting code. The encoding can include inverting the plurality of binary data bits and adding an inversion data bit to the information word.

公开(公告)号：US20250036305A1

公开(公告)日：2025-01-30

申请号：US18794882

申请日：2024-08-05

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Thomas Hein

IPC: G06F3/06

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

公开(公告)号：US12079508B2

公开(公告)日：2024-09-03

申请号：US17868041

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Thomas Hein

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

公开(公告)号：US12007839B2

公开(公告)日：2024-06-11

申请号：US17732289

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Thomas Hein

IPC: H03M13/27 ,  G06F11/07 ,  G06F11/10 ,  G06F13/16 ,  G06F13/28 ,  H03M13/25 ,  H04L1/00 ,  H04L27/34

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/0787

Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.