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公开(公告)号：US10854310B2
公开(公告)日：2020-12-01
申请号：US16436767
申请日：2019-06-10
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono , Taihei Shido , Yuki Ebihara
Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
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公开(公告)号：US20190295679A1
公开(公告)日：2019-09-26
申请号：US16436767
申请日：2019-06-10
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono , Taihei Shido , Yuki Ebihara
Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
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公开(公告)号：US10304505B2
公开(公告)日：2019-05-28
申请号：US16133576
申请日：2018-09-17
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.
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公开(公告)号：US20180151207A1
公开(公告)日：2018-05-31
申请号：US15365563
申请日：2016-11-30
Applicant: Micron Technology, Inc.
Inventor： Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
CPC classification number: G11C7/1087 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C19/28 , G11C2207/108 , G11C2207/2272
Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号：US10163469B2
公开(公告)日：2018-12-25
申请号：US15365563
申请日：2016-11-30
Applicant: Micron Technology, Inc.
Inventor： Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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Patent Agency Ranking
公开(公告)号：US20180261273A1
公开(公告)日：2018-09-13
申请号：US15979057
申请日：2018-05-14
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
IPC: G11C11/406 , G11C11/408 , G11C11/4076
CPC classification number: G11C11/406 , G11C7/222 , G11C11/40603 , G11C11/4076 , G11C11/4087 , G11C11/4093
Abstract: Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
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7.发明申请公开(公告)号：US20160034340A1
公开(公告)日：2016-02-04
申请号：US14678375
申请日：2015-04-03
Applicant: Micron Technology, Inc.
Inventor： CHIAKI DONO , Seiichi Maruno , Taihei Shido , Toshio Ninomiya , Chikara Kondo
IPC: G06F11/10
CPC classification number: G06F11/1004 , G06F11/1016
Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit, The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and as data bus invasion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
Abstract translation: 一种装置包括第一外部终端，第一电路，信号线和第二电路。第一外部终端接收数据掩码信息和数据总线反转信息中的至少一个。 第一个电路执行错误检查操作和数据总线入侵操作之一。 信号线耦合在第一外部端子和第一电路之间。 第二电路耦合到信号线，并且首先响应于第一控制信号，以基本上恒定的电平将信号线的电压电平耦合。
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公开(公告)号：US10338997B2
公开(公告)日：2019-07-02
申请号：US15983073
申请日：2018-05-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chiaki Dono , Seiichi Maruno , Taihei Shido , Toshio Ninomiya , Chikara Kondo
Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
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公开(公告)号：US10079049B2
公开(公告)日：2018-09-18
申请号：US15176442
申请日：2016-06-08
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.
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公开(公告)号：US20170358336A1
公开(公告)日：2017-12-14
申请号：US15176442
申请日：2016-06-08
Applicant: Micron Technology, Inc.
Inventor： Taihei Shido
CPC classification number: G11C7/22 , G06F13/16 , G11C7/10 , G11C7/1069 , G11C7/109 , G11C7/1096
Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.
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