-
公开(公告)号：US20240212752A1
公开(公告)日：2024-06-27
申请号：US18518126
申请日：2023-11-22
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Umberto Di Vincenzo , Michele Maria Venturini
IPC: G11C13/04 , H03K17/687
CPC classification number: G11C13/042 , H03K17/687
Abstract: A detection circuit may be configured to receive an input signal indicative of a data state and to detect the data state using charge sharing between two capacitors to achieve detection with threshold compensation . The detection circuit may include semi-latch circuitry and boosting circuitry to expedite the detection, thereby achieving high speed at low power consumption and low circuit size.
-
公开(公告)号：US20240194272A1
公开(公告)日：2024-06-13
申请号：US18586134
申请日：2024-02-23
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.
-
公开(公告)号：US20230282301A1
公开(公告)日：2023-09-07
申请号：US18112307
申请日：2023-02-21
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
CPC classification number: G11C29/42 , G11C29/44 , G11C7/14 , G11C29/20 , G11C29/12005
Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.
-
公开(公告)号：US20230206978A1
公开(公告)日：2023-06-29
申请号：US17646259
申请日：2021-12-28
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Michele Maria Venturini
IPC: G11C11/22 , G11C7/12 , H01L27/11514
CPC classification number: G11C11/2273 , G11C11/221 , G11C7/12 , H01L27/11514
Abstract: Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.
-
公开(公告)号：US11670368B2
公开(公告)日：2023-06-06
申请号：US17512586
申请日：2021-10-27
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
CPC classification number: G11C13/004 , G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0045
Abstract: A method for reading memory cells is described. The method may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.
-
Patent Agency Ranking
公开(公告)号：US11594297B2
公开(公告)日：2023-02-28
申请号：US17590532
申请日：2022-02-01
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.
-
公开(公告)号：US11587604B2
公开(公告)日：2023-02-21
申请号：US17241889
申请日：2021-04-27
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Ferdinando Bedeschi , Riccardo Muzzetto
IPC: G11C11/22
Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.
-
公开(公告)号：US11545219B2
公开(公告)日：2023-01-03
申请号：US16975619
申请日：2020-03-24
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Efrem Bolandrina , Umberto Di Vincenzo , Riccardo Muzzetto
Abstract: A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.
-
公开(公告)号：US11335408B2
公开(公告)日：2022-05-17
申请号：US17200385
申请日：2021-03-12
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Umberto Di Vincenzo
IPC: G11C11/34 , G11C16/12 , G11C16/28 , G11C7/14 , G11C11/24 , G11C7/06 , G11C11/404 , G11C13/00 , G11C11/56
Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.
-
公开(公告)号：US20220122659A1
公开(公告)日：2022-04-21
申请号：US17512586
申请日：2021-10-27
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
IPC: G11C13/00
Abstract: The present disclosure relates to a method for reading memory cells, and may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.
-
-
-
-
-
-
-
-
-
Search Results
178
records
(took 0.029 seconds)
