公开(公告)号：US10614024B2

公开(公告)日：2020-04-07

申请号：US15987895

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G11C11/00 ,  G06F13/42 ,  G11C11/4093 ,  G11C11/402 ,  H01L27/108

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US11805638B2

公开(公告)日：2023-10-31

申请号：US17202144

申请日：2021-03-15

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Yuki Ebihara

IPC: G11C19/08 ,  H10B12/00 ,  G11C11/4074 ,  G11C19/28 ,  G06F5/06

CPC classification number: H10B12/315 ,  G06F5/06 ,  G11C11/4074 ,  G11C19/0875 ,  G11C19/287

Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

公开(公告)号：US10664432B2

公开(公告)日：2020-05-26

申请号：US15987895

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G11C11/00 ,  G06F13/42 ,  G11C11/4093 ,  G11C11/402 ,  H01L27/108

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US20190361835A1

公开(公告)日：2019-11-28

申请号：US15987895

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G06F13/42 ,  H01L27/108 ,  G11C11/402 ,  G11C11/4093

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US20180025789A1

公开(公告)日：2018-01-25

申请号：US15217719

申请日：2016-07-22

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Taihei Shido ,  Yuki Ebihara

IPC: G11C29/38 ,  G11C29/44 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C29/1201 ,  G11C29/36 ,  G11C29/44 ,  G11C29/48 ,  G11C29/76

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

公开(公告)号：US20210225848A1

公开(公告)日：2021-07-22

申请号：US17202144

申请日：2021-03-15

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Yuki Ebihara

IPC: H01L27/108 ,  G11C11/4074 ,  G11C19/08 ,  G11C19/28 ,  G06F5/06

Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

公开(公告)号：US10854310B2

公开(公告)日：2020-12-01

申请号：US16436767

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Taihei Shido ,  Yuki Ebihara

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/44 ,  G11C29/12 ,  G11C29/48

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

公开(公告)号：US20190295679A1

公开(公告)日：2019-09-26

申请号：US16436767

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Taihei Shido ,  Yuki Ebihara

IPC: G11C29/38 ,  G11C29/00 ,  G11C29/48 ,  G11C29/36 ,  G11C29/44 ,  G11C29/12

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

公开(公告)号：US10964702B2

公开(公告)日：2021-03-30

申请号：US16163471

申请日：2018-10-17

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Yuki Ebihara

IPC: G06F5/06 ,  H01L27/108 ,  G11C11/4074 ,  G11C19/08 ,  G11C19/28

Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

公开(公告)号：US10922262B2

公开(公告)日：2021-02-16

申请号：US16840281

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G11C7/00 ,  G06F13/42 ,  G11C11/4093 ,  G11C11/402 ,  H01L27/108

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.