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公开(公告)号：US10007235B2
公开(公告)日：2018-06-26
申请号：US15711012
申请日：2017-09-21
CPC分类号： G04F10/005 , H03M1/1009 , H03M1/125 , H03M1/502
摘要： A time-to-digital converter (TDC) measures a time interval ΔTTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=ΔTTot−mTNOR to obtain a value for the time interval ΔTTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.
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公开(公告)号：US20180088535A1
公开(公告)日：2018-03-29
申请号：US15711012
申请日：2017-09-21
IPC分类号： G04F10/00
CPC分类号： G04F10/005 , H03M1/1009 , H03M1/125 , H03M1/502
摘要： A time-to-digital converter (TDC) measures a time interval ΔTTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=ΔTTot−mTNOR to obtain a value for the time interval ΔTTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.
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公开(公告)号：US09584138B2
公开(公告)日：2017-02-28
申请号：US15091269
申请日：2016-04-05
发明人： Krste Mitric , Qu Gary Jin , Guohui Situ , Paul H. L. M. Schram , Changhui Cathy Zhang , Richard Geiss
CPC分类号： H03L7/07 , H03L7/093 , H03L7/0991 , H03L7/23 , H04L5/06
摘要： A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
摘要翻译： 多通道锁相环（PLL）装置具有多个PLL通道。 每个通道包括数字控制振荡器（DCO），通过输出分频器将输出时钟提供给相应的输出引脚。 第一个复用器选择任何PLL通道进行对准。 反馈校准PLL响应于在相应的输出引脚从所选通道的输出时钟导出的反馈信号。 延迟控制模块响应反馈校准PLL的输出来调整输出时钟的相位。
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公开(公告)号：US20160301417A1
公开(公告)日：2016-10-13
申请号：US15091269
申请日：2016-04-05
发明人： Krste Mitric , Qu Gary Jin , Guohui Situ , Paul H.L.M. Schram , Changhui Cathy Zhang , Richard Geiss
CPC分类号： H03L7/07 , H03L7/093 , H03L7/0991 , H03L7/23 , H04L5/06
摘要： A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
摘要翻译： 多通道锁相环（PLL）装置具有多个PLL通道。 每个通道包括数字控制振荡器（DCO），通过输出分频器将输出时钟提供给相应的输出引脚。 第一个复用器选择任何PLL通道进行对准。 反馈校准PLL响应于在相应的输出引脚从所选通道的输出时钟导出的反馈信号。 延迟控制模块响应反馈校准PLL的输出来调整输出时钟的相位。
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公开(公告)号：US20160294393A1
公开(公告)日：2016-10-06
申请号：US15088188
申请日：2016-04-01
发明人： Slobodan Milijevic , Guohui Situ
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509
摘要： A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. The multiplexer is responsive to a selection signal to select either of the first and second inputs of said multiplexer. A pair of single-input buffers have inputs coupled respectively to the first and second input pins. A first input of a first differential buffer is coupled to the first input pin, a first input of a second differential buffer is coupled to the second input pin, the second input of the first differential buffer is coupled to the output of the multiplexer, and the second input of the second differential buffer receives a common mode voltage of a differential signal applied to the second pin.
摘要翻译： 通用输入缓冲器有一对输入引脚。 多路复用器的第一输入耦合到第二输入引脚，并且多路复用器的第二输入接收施加到第一引脚的差分信号的共模电压。 复用器响应于选择信号来选择所述多路复用器的第一和第二输入中的任一个。 一对单输入缓冲器具有分别耦合到第一和第二输入引脚的输入。 第一差分缓冲器的第一输入耦合到第一输入引脚，第二差分缓冲器的第一输入耦合到第二输入引脚，第一差分缓冲器的第二输入耦合到多路复用器的输出端，以及 第二差分缓冲器的第二输入接收施加到第二引脚的差分信号的共模电压。
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公开(公告)号：US09444461B1
公开(公告)日：2016-09-13
申请号：US15088188
申请日：2016-04-01
发明人： Slobodan Milijevic , Guohui Situ
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509
摘要： A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. The multiplexer is responsive to a selection signal to select either of the first and second inputs of said multiplexer. A pair of single-input buffers have inputs coupled respectively to the first and second input pins. A first input of a first differential buffer is coupled to the first input pin, a first input of a second differential buffer is coupled to the second input pin, the second input of the first differential buffer is coupled to the output of the multiplexer, and the second input of the second differential buffer receives a common mode voltage of a differential signal applied to the second pin.
摘要翻译： 通用输入缓冲器有一对输入引脚。 多路复用器的第一输入耦合到第二输入引脚，并且多路复用器的第二输入接收施加到第一引脚的差分信号的共模电压。 复用器响应于选择信号来选择所述多路复用器的第一和第二输入中的任一个。 一对单输入缓冲器具有分别耦合到第一和第二输入引脚的输入。 第一差分缓冲器的第一输入耦合到第一输入引脚，第二差分缓冲器的第一输入耦合到第二输入引脚，第一差分缓冲器的第二输入耦合到多路复用器的输出端，以及 第二差分缓冲器的第二输入接收施加到第二引脚的差分信号的共模电压。
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