公开(公告)号：US10565129B2

公开(公告)日：2020-02-18

申请号：US15637685

申请日：2017-06-29

Applicant: Microsoft Technology Licensing, LLC

Inventor： Felix Schuster ,  Olga Ohrimenko ,  Istvan Haller ,  Manuel Silverio da Silva Costa ,  Daniel Gruss ,  Julian Lettner

IPC: G06F12/14 ,  G06F12/128 ,  G06F9/46 ,  G06F12/0806

Abstract: In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.

公开(公告)号：US20180341600A1

公开(公告)日：2018-11-29

申请号：US15637685

申请日：2017-06-29

Applicant: Microsoft Technology Licensing, LLC

Inventor： Felix Schuster ,  Olga Ohrimenko ,  Istvan Haller ,  Manuel Silverio da Silva Costa ,  Daniel Gruss ,  Julian Lettner

IPC: G06F12/14 ,  G06F12/128 ,  G06F9/46 ,  G06F12/0806

CPC classification number: G06F12/14 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/128 ,  G06F12/1441 ,  G06F21/53 ,  G06F21/74 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/452 ,  G06F2212/621

Abstract: In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.