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107 条记录 (耗时 0.03 秒)

    Low-k spacer integration into CMOS transistors
    3.
    发明申请
    Low-k spacer integration into CMOS transistors 审中-公开
    低k隔离器集成到CMOS晶体管中

    公开(公告)号：US20070202640A1

    公开(公告)日：2007-08-30

    申请号：US11365740

    申请日：2006-02-28

    申请人： Amir Al-Bayati ,  Reza Arghavani ,  Mei-Yee Shek ,  Li-Qun Xia ,  Mihaela Balseanu ,  Bok Kim ,  Michael Cox ,  Chad Peterson ,  Hichem M'Saad

    发明人： Amir Al-Bayati ,  Reza Arghavani ,  Mei-Yee Shek ,  Li-Qun Xia ,  Mihaela Balseanu ,  Bok Kim ,  Michael Cox ,  Chad Peterson ,  Hichem M'Saad

    IPC分类号： H01L21/338

    CPC分类号： H01L29/4983 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/26586 ,  H01L21/3146 ,  H01L21/31633 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

    摘要： A method of forming source and drain regions in a semiconductor transistor. The method includes the steps of forming a first sidewall spacer on sidewall surfaces of a gate electrode that is formed on an underlying substrate, where the first sidewall spacer includes amorphous carbon. The method may also include implanting the source and drain regions in the semiconductor substrate, and removing the first sidewall spacer before annealing the source and drain regions. The method may still further include forming a second sidewall spacer on the sidewall surfaces of the gate electrode, where the second sidewall spacer has a k-value less than 4. Also, a method to enhance conformality of a sidewall spacer layer. The method may include the steps of pulsing a radio-frequency power source to generate periodically a plasma, and depositing the plasma on sidewall surfaces of a gate electrode to form the sidewall spacer layer.

    摘要翻译： 一种在半导体晶体管中形成源区和漏区的方法。 该方法包括以下步骤：在形成在下面的基底上的栅电极的侧壁表面上形成第一侧壁间隔物，其中第一侧壁间隔物包括无定形碳。 该方法还可以包括将源极和漏极区域注入到半导体衬底中，以及在退火源极和漏极区域之前去除第一侧壁间隔物。 该方法还可以包括在栅电极的侧壁表面上形成第二侧壁间隔物，其中第二侧壁间隔物的k值小于4.另外，增强侧壁间隔层的一致性的方法。 该方法可以包括以下步骤：脉冲射频电源周期性地产生等离子体，以及将等离子体沉积在栅电极的侧壁表面上以形成侧壁间隔层。

    Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay
    8.
    发明授权
    Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay 有权
    在电介质层中产生气隙以减少RC延迟的方法和装置

    公开(公告)号：US07879683B2

    公开(公告)日：2011-02-01

    申请号：US11869396

    申请日：2007-10-09

    申请人： Amir Al-Bayati ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang “David” Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

    发明人： Amir Al-Bayati ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang “David” Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

    IPC分类号： H01L21/76

    CPC分类号： H01L21/7682 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.

    摘要翻译： 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。

    FLASH MEMORY WITH TREATED CHARGE TRAP LAYER
    10.
    发明申请
    FLASH MEMORY WITH TREATED CHARGE TRAP LAYER 失效
    具有处理充电陷阱层的闪存

    公开(公告)号：US20100099247A1

    公开(公告)日：2010-04-22

    申请号：US12256173

    申请日：2008-10-22

    申请人： Mihaela Balseanu ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

    发明人： Mihaela Balseanu ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

    IPC分类号： H01L21/28

    CPC分类号： H01L21/3185 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792

    摘要： A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

    摘要翻译： 提供了形成闪速存储器件的方法。 闪存器件包括在衬底上的二氧化硅层和形成在二氧化硅层上的氮化硅层。 氮化硅层的性质可以通过以下任何方式改变：将氮化硅层暴露于紫外线辐射，将氮化硅层暴露于电子束，以及通过等离子体处理氮化硅层。 介电材料沉积在氮化硅层上，并且在电介质材料上形成导电日期。 具有改进的氮化硅层的闪速存储器件提供了非易失性存储器件的单元电池的电荷保持容量和电荷保持时间的增加。