公开(公告)号：US20060249829A1

公开(公告)日：2006-11-09

申请号：US11399608

申请日：2006-04-07

申请人： Mitsuaki Katagiri ,  Masanori Shibamoto ,  Tsutomu Hara ,  Koichiro Aoki ,  Naoya Kanda ,  Shuji Kikuchi ,  Hisashi Tanie

发明人： Mitsuaki Katagiri ,  Masanori Shibamoto ,  Tsutomu Hara ,  Koichiro Aoki ,  Naoya Kanda ,  Shuji Kikuchi ,  Hisashi Tanie

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/50 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the connecting terminals and external terminals; semiconductor chips having a pad row in which pads is arranged linearly in parallel to the terminal row and being stacked on the baseboard; and interposer boards having a wiring layer including a plurality of wires arranged in parallel with the same length for connecting between pads of the pad row and connecting terminals of the terminal row.

摘要翻译： 一种叠层型半导体器件，包括：基板，其端部形成在端部，所述端子排连接端子线性布置，并且具有连接到所述连接端子和外部端子的布线图案; 具有垫排的半导体芯片，其中焊盘与端子排平行布置并且堆叠在基板上; 以及具有布线层的插入板，所述布线层包括以相同长度平行布置的多条布线，用于连接所述焊盘排的焊盘和所述端子排的连接端子。

公开(公告)号：US07546506B2

公开(公告)日：2009-06-09

申请号：US11378368

申请日：2006-03-20

申请人： Yuji Sonoda ,  Shuji Kikuchi ,  Katsunori Hirano ,  Ichiro Anjo ,  Mitsuaki Katagiri

发明人： Yuji Sonoda ,  Shuji Kikuchi ,  Katsunori Hirano ,  Ichiro Anjo ,  Mitsuaki Katagiri

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C5/04 ,  G11C2029/2602 ,  G11C2029/5602

摘要： The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

摘要翻译： 本发明涉及一种DRAM堆叠封装，一种DIMM，一种用于测试它们的方法以及一种半导体制造方法。 根据本发明，提供了一种DRAM堆叠封装，包括：多个堆叠的DRAM; 连接测试设备的外部终端，所述外部终端至少用于输入/输出地址，命令和数据; 以及设置在所述多个堆叠的DRAM和所述外部端子之间的接口芯片。 多个DRAM和接口芯片被实现在封装上。 接口芯片包括：测试电路，包括：算法模式发生器，用于产生用于测试多个DRAM的测试模式; 施加用于将所述生成的测试图案应用于所述多个DRAM的电路; 以及用于将从多个DRAM接收的每个响应信号与用于判断的期望值进行比较的比较器。

公开(公告)号：US20060239055A1

公开(公告)日：2006-10-26

申请号：US11378368

申请日：2006-03-20

申请人： Yuji Sonoda ,  Shuji Kikuchi ,  Katsunori Hirano ,  Ichiro Anjo ,  Mitsuaki Katagiri

发明人： Yuji Sonoda ,  Shuji Kikuchi ,  Katsunori Hirano ,  Ichiro Anjo ,  Mitsuaki Katagiri

IPC分类号： G11C5/02

CPC分类号： G11C29/48 ,  G11C5/04 ,  G11C2029/2602 ,  G11C2029/5602

摘要： The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

公开(公告)号：US08168950B2

公开(公告)日：2012-05-01

申请号：US12273805

申请日：2008-11-19

申请人： Kanji Furuhashi ,  Shuji Kikuchi ,  Akira Karakama ,  Yasuhiro Gunji

发明人： Kanji Furuhashi ,  Shuji Kikuchi ,  Akira Karakama ,  Yasuhiro Gunji

IPC分类号： H01J37/28

CPC分类号： H01J37/28 ,  H01J37/20 ,  H01J37/265 ,  H01J2237/20221 ,  H01J2237/20278 ,  H01J2237/2817

摘要： The present invention has a subject to provide an apparatus that optimizes scanning in accordance with circumstances or purposes, reduces distortion of images, and improves throughput, image quality, and defect detection rate by controlling deflection of a charged particle beam in a stage tracking system. To solve this subject, an apparatus according to the present invention is an inspection apparatus for detecting abnormal conditions of an inspection target by irradiating the inspection target with the charged particle beam and detecting generated secondary electrons, including both a stage that moves continuously with the inspection target placed thereon and a deflection control circuit for providing a deflector with a scanning signal that causes the charged particle beam to scan repeatedly in a direction substantially perpendicular to a stage movement axis direction while the charged particle beam being deflected in the stage movement axis direction in accordance with a change in movement speed of the stage during movement of the stage.

摘要翻译： 本发明提供一种根据情况或目的优化扫描的装置，减少图像的失真，并且通过控制在舞台跟踪系统中的带电粒子束的偏转来提高吞吐量，图像质量和缺陷检测率。 为了解决这个问题，根据本发明的装置是一种检查装置，用于通过用带电粒子束照射检查对象并检测产生的二次电子来检测检查对象的异常状况，包括两个检查阶段连续移动的阶段 目标物放置在其上，以及偏转控制电路，用于向偏转器提供扫描信号，该扫描信号使得带电粒子束在基本上垂直于载物台移动轴线方向的方向上反复扫描，同时带电粒子束在载物台移动轴线方向上偏转 根据舞台运动中舞台的移动速度的变化。

公开(公告)号：US4759021A

公开(公告)日：1988-07-19

申请号：US920986

申请日：1986-09-30

申请人： Ikuo Kawaguchi ,  Masaaki Inadachi ,  Shuji Kikuchi

发明人： Ikuo Kawaguchi ,  Masaaki Inadachi ,  Shuji Kikuchi

IPC分类号： G01R31/319 ,  G06F11/22

CPC分类号： G01R31/31921

摘要： In a semiconductor testing device of LSI or the like, a high-speed small-capacity memory (50) is provided in addition to low-speed large-capacity memories (11.about.14) for interleave operation, and test patterns after a branch operation are previously stored in the memory (50). When test patterns are to be read in sequence the reading is performed from the low-speed large-capacity memories (11.about.14), and when branch is produced in the reading sequence the changing is performed to the high-speed small-capacity memory (50) and the test patterns are read from the high-speed small-capacity memory (50) until the reading from the low-speed large-capacity memories (11.about.14) again becomes possible. Thereby, the test patterns of a large number can be outputted without generating a dummy cycle.

摘要翻译： PCT No.PCT / JP86 / 00039 Sec。 371日期1986年9月30日第 102（e）1986年9月30日PCT申请人1986年1月31日PCT公布。 出版物WO86 / 04686 日本1986年8月14日。在LSI等的半导体测试装置中，除了用于交错操作的低速大容量存储器（11差分14）之外还提供高速小容量存储器（50） 并且分支操作之后的测试模式预先存储在存储器（50）中。 当要读取测试图案时，从低速大容量存储器（11差分14）进行读取，并且当在读取顺序中产生分支时，对高速小容量存储器 （50），并且从高速小容量存储器（50）读取测试图案，直到从低速大容量存储器（11差分14）读取再次变为可能。 因此，可以输出大量的测试图案而不产生虚拟周期。

公开(公告)号：US20130108905A1

公开(公告)日：2013-05-02

申请号：US13661611

申请日：2012-10-26

申请人： Manabu Murakami ,  Shigenori Kawana ,  Sakae Kawashima ,  Shuji Kikuchi

发明人： Manabu Murakami ,  Shigenori Kawana ,  Sakae Kawashima ,  Shuji Kikuchi

IPC分类号： H01M10/48

CPC分类号： H01M10/425 ,  H01M2/1077 ,  H01M2/206 ,  H01M10/482 ,  H01M2220/10

摘要： According to one embodiment, a unit includes battery modules each including an assembled battery including battery cells and a monitoring device, a BMU to communicate with the battery modules, a first drawer holding the battery module, a second drawer holding the BMU, and a housing containing the first drawer and the second drawer. The first and second drawers include first composite connectors secured to a side of the housing, which is almost orthogonal to a direction in which to insert the drawers into the housing. The housing has second composite connectors which mate with the first composite connectors, thereby to connect communication lines between the monitoring device and the BMU and the main-circuit lines between the assembled batteries of the battery modules.

摘要翻译： 根据一个实施例，一个单元包括电池模块，每个电池模块包括包括电池单元和监视装置的组合电池，与电池模块通信的BMU，保持电池模块的第一抽屉，保持BMU的第二抽屉和壳体 包含第一个抽屉和第二个抽屉。 第一和第二抽屉包括固定到壳体一侧的第一复合连接器，其几乎与将抽屉插入壳体的方向正交。 壳体具有与第一复合连接器配合的第二复合连接器，从而将监视装置和BMU之间的通信线与电池模块的组合电池之间的主电路线连接起来。

公开(公告)号：US08032332B2

公开(公告)日：2011-10-04

申请号：US12099868

申请日：2008-04-09

申请人： Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

发明人： Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

IPC分类号： G06F11/00 ,  G01R31/00

CPC分类号： G06F13/4045 ,  G01N21/95684

摘要： A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

摘要翻译： 半导体检查装置包括：缓冲存储器，其宽度与并行总线宽度越大并且串行数量的宽度相匹配; 前级总线切换单元，其不输入空闲空间来填充缓冲存储器中的输入数据; 等效传输容量转换，包括后级总线切换单元，其将读取的数据填充到任意数量的串行通道的宽度而不产生空闲空间; 前级总线切换单元，其不输入空闲空间来填充具有输入数据的缓冲存储器; 以及等效传输容量逆变换，包括后级总线切换单元，其填充具有从缓冲存储器读取的数据的任意宽度的并行总线，而不产生空闲空间。

公开(公告)号：US06826720B2

公开(公告)日：2004-11-30

申请号：US09994638

申请日：2001-11-28

申请人： Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

发明人： Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

IPC分类号： G11C2900

CPC分类号： G11C29/56 ,  G11C29/10

摘要： A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

摘要翻译： 使用ALPG的测试电路安装在测试板中，其中安装半导体存储器的插座作为板中要测试的器件，并且在测试电路中提供用于存储用于产生随机模式的数据表的易失性存储器，使得 除了使用由ALPG生成的规则性的测试图案的测试之外，还使用数据表来执行使用不规则的测试图案的测试。

公开(公告)号：US5343047A

公开(公告)日：1994-08-30

申请号：US82454

申请日：1993-06-25

申请人： Hiroo Ono ,  Shuji Kikuchi ,  Masayuki Tomoyasu ,  Naoki Takayama ,  Riki Tomoyoshi

发明人： Hiroo Ono ,  Shuji Kikuchi ,  Masayuki Tomoyasu ,  Naoki Takayama ,  Riki Tomoyoshi

IPC分类号： H01J37/317

CPC分类号： H01J37/3171 ,  H01J2237/24405 ,  H01J2237/24507 ,  H01J2237/31703

摘要： A system for implanting ions into a semiconductor wafer includes an ion source device, a mass spectrometer, an accelerating tube and a process chamber arranged in this order. A rotating disk is arranged in the process chamber to support a plurality of wafers thereon. A Faraday cup is arranged in the process chamber, corresponding to an ion beam shooting position. The Faraday cup serves to shut up therein secondary electrons and ions generated from the wafer at the time of ion implantation for measuring the amount of ions implanted. A suppressor electrode is provided to suppress the flow-out of the secondary electrons from the Faraday cup. The suppressor electrode comprises a cylindrical body made of carbon and an SiC film formed on the inner face of the cylindrical body. The SiC film serves as a resistance of the electrode surface for preventing rapid discharge from being caused at the electrode surface.

摘要翻译： 用于将离子注入半导体晶片的系统包括依次布置的离子源装置，质谱仪，加速管和处理室。 旋转盘布置在处理室中以在其上支撑多个晶片。 法拉第杯布置在处理室中，对应于离子束拍摄位置。 法拉第杯用于在离子注入时闭合从晶片产生的二次电子和离子，以测量植入的离子的量。 提供抑制电极以抑制来自法拉第杯的二次电子的流出。 抑制电极包括由碳制成的圆柱体和形成在圆柱体的内表面上的SiC膜。 SiC膜用作电极表面的电阻，用于防止在电极表面处引起快速放电。

公开(公告)号：US08653458B2

公开(公告)日：2014-02-18

申请号：US13812121

申请日：2011-06-22

申请人： Yoshiro Gunji ,  Shuji Kikuchi

发明人： Yoshiro Gunji ,  Shuji Kikuchi

IPC分类号： G01N23/00

CPC分类号： H01J37/261 ,  H01J37/1474 ,  H01J37/265 ,  H01J37/28

摘要： An inspection device carries out beam scanning on a stable scanning cycle by enabling flexible change of various scanning sequences according to inspection conditions thereof, and at the same time, eliminates as much unevenness as possible in scanning cycle which hinders stabilization of charging. A beam scanning scheduler schedules beam scanning based on an inputted scanning condition, and a programmable sequencer carries out beam scanning control according to a beam scanning schedule generated by the beam scanning scheduler. The scanning scheduler calculates scanning line reference coordinates on a scanning-line-by-scanning-line basis, based on the scanning condition, and issues a scanning cycle trigger. The programmable sequencer controls supply timing of the scanning line reference coordinates and a scanning position on an in-line pixel-by-pixel basis, based on line scanning procedure information and the scanning cycle trigger provided from the beam scanning scheduler.

摘要翻译： 检查装置通过根据其检查条件灵活地改变各种扫描序列，在稳定的扫描周期进行光束扫描，并且同时消除了妨碍充电稳定性的扫描周期中尽可能多的不均匀性。 光束扫描调度器基于输入的扫描条件调度波束扫描，并且可编程序定序器根据由波束扫描调度器生成的波束扫描调度执行波束扫描控制。 扫描调度器基于扫描条件在逐行扫描线上计算扫描线参考坐标，并发出扫描周期触发。 基于行扫描程序信息和从波束扫描调度器提供的扫描周期触发，可编程序器根据逐行逐像素地控制扫描线参考坐标的提供定时和扫描位置。