公开(公告)号：US08380917B2

公开(公告)日：2013-02-19

申请号：US12138307

申请日：2008-06-12

申请人： Kenji Shibata ,  Mitsuhiro Nagao ,  Satoru Kawmoto

发明人： Kenji Shibata ,  Mitsuhiro Nagao ,  Satoru Kawmoto

IPC分类号： G06F12/00 ,  G06F13/28 ,  G06F13/00

CPC分类号： G11C16/10 ,  G11C7/10 ,  G11C7/1072

摘要： Systems, methods, and circuits for command control for synchronous memory device are disclosed. In one embodiment, a memory device comprises a first synchronous memory controlled by a second group of commands which includes a first command receiving section for receiving a first group of commands, and a second command receiving section for receiving a command that is unique to the first synchronous memory and different from the first group of commands during execution of the first group of commands received by the first command receiving section. The synchronous memory further comprises a second synchronous memory controlled by the first group of commands, where the first synchronous memory and the second synchronous memory are coupled to a same data bus, and where the second group of commands is different from the first group of commands.

摘要翻译： 公开了用于同步存储装置的命令控制的系统，方法和电路。 在一个实施例中，存储器设备包括由第二组命令控制的第一同步存储器，该第二组命令包括用于接收第一组命令的第一命令接收部分和用于接收第一命令的唯一命令的第二命令接收部分 同步存储器，并且在执行由第一命令接收部分接收的第一组命令期间与第一组命令不同。 同步存储器还包括由第一组命令控制的第二同步存储器，其中第一同步存储器和第二同步存储器耦合到相同的数据总线，并且其中第二组命令与第一组命令不同 。

公开(公告)号：US08122204B2

公开(公告)日：2012-02-21

申请号：US12137443

申请日：2008-06-11

申请人： Mitsuhiro Nagao ,  Kenji Shibata ,  Satoru Kawmoto

发明人： Mitsuhiro Nagao ,  Kenji Shibata ,  Satoru Kawmoto

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F1/00 ,  G06F3/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： G06F13/1694 ,  G06F11/1666 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40622 ,  G11C11/4096 ,  Y02D10/14

摘要： Systems and methods for controlling memory devices are disclosed. In one embodiment, a memory system comprises a memory controller for forwarding a command signal and an address signal and for receiving and forwarding a data signal, and a first memory device for receiving the command signal and the address signal from the memory controller, where the first memory device comprises a first command judging circuit for receiving and forwarding the data signal and for decoding the command signal. The memory system further comprises a second memory device for receiving the command signal and the address signal from the memory controller, where the second memory device comprises a second command judging circuit for receiving and generating the data signal and for decoding the command signal. The command signal, the address signal and the data signal are commonly connected to the first memory device and the second memory device.

摘要翻译： 公开了用于控制存储器件的系统和方法。 在一个实施例中，存储器系统包括用于转发命令信号和地址信号并用于接收和转发数据信号的存储器控​​制器，以及用于从存储器控制器接收命令信号和地址信号的第一存储器件，其中 第一存储装置包括用于接收和转发数据信号并用于对命令信号进行解码的第一命令判断电路。 存储器系统还包括用于从存储器控制器接收命令信号和地址信号的第二存储器件，其中第二存储器件包括用于接收和产生数据信号并用于解码命令信号的第二命令判断电路。 命令信号，地址信号和数据信号共同连接到第一存储器件和第二存储器件。

公开(公告)号：US20080155217A1

公开(公告)日：2008-06-26

申请号：US11644161

申请日：2006-12-22

申请人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

发明人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F2212/2022

摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.

摘要翻译： 半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

公开(公告)号：US07934051B2

公开(公告)日：2011-04-26

申请号：US12012390

申请日：2008-02-01

申请人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

发明人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

IPC分类号： G06F12/00

CPC分类号： G11C16/22

摘要： The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region.

摘要翻译： 本发明提供半导体器件和控制半导体器件的方法，该半导体器件包括包括非易失性存储器单元的存储区域; 程序禁止信息单元，程序禁止信息单元存储要用于确定是否禁止或允许在对应于程序禁止信息单元的多个存储器区域中进行编程的程序禁止信息; 第一禁止信息控制电路，禁止将程序禁止信息从程序禁止状态改变为允许相对于存储区域的状态的程序，所述存储区域是所述多个对应的存储区域中的一个，基于第一禁止信息 用于确定是否禁止将程序禁止信息从程序禁止状态改变为相对于对应的存储区域的程序允许状态; 以及第二禁止信息控制电路，其基于第二禁止信息来禁止程序禁止信息从允许状态到相对于存储区域的程序禁止状态的程序的改变，所述第二禁止信息控制电路用于确定是否禁止改变 程序禁止信息从允许状态到相对于对应的存储器区域的程序禁止状态的程序。

公开(公告)号：US20090049253A1

公开(公告)日：2009-02-19

申请号：US12012390

申请日：2008-02-01

申请人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

发明人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

IPC分类号： G06F12/00

CPC分类号： G11C16/22

摘要： The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region

摘要翻译： 本发明提供半导体器件和控制半导体器件的方法，该半导体器件包括包括非易失性存储器单元的存储区域; 程序禁止信息单元，程序禁止信息单元存储要用于确定是否禁止或允许在对应于程序禁止信息单元的多个存储器区域中进行编程的程序禁止信息; 第一禁止信息控制电路，禁止将程序禁止信息从程序禁止状态改变为允许相对于存储区域的状态的程序，所述存储区域是所述多个对应的存储区域中的一个，基于第一禁止信息 用于确定是否禁止将程序禁止信息从程序禁止状态改变为相对于对应的存储区域的程序允许状态; 以及第二禁止信息控制电路，其基于第二禁止信息来禁止程序禁止信息从允许状态到相对于存储区域的程序禁止状态的程序的改变，所述第二禁止信息控制电路用于确定是否禁止改变 程序禁止信息从允许状态到相对于对应的存储器区域的程序禁止状态的程序

公开(公告)号：US07574576B2

公开(公告)日：2009-08-11

申请号：US11644161

申请日：2006-12-22

申请人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

发明人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

IPC分类号： G06F12/00

CPC分类号： G06F12/1425 ,  G06F2212/2022

摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.

摘要翻译： 半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

公开(公告)号：US08219743B2

公开(公告)日：2012-07-10

申请号：US13052486

申请日：2011-03-21

申请人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

发明人： Kenji Shibata ,  Masahiko Okura ,  Mitsuhiro Nagao

IPC分类号： G06F12/00

CPC分类号： G11C16/22

摘要： The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions; program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in the memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state with respect to a memory region based on first prohibition information; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region based on second prohibition information with respect to the corresponding memory region.

摘要翻译： 本发明提供半导体器件和控制半导体器件的方法，该半导体器件包括存储区域; 程序禁止信息单元存储用于确定是否禁止或允许对应于程序禁止信息单元的存储器区域中的编程的程序禁止信息; 第一禁止信息控制电路，基于第一禁止信息禁止程序禁止信息相对于存储区域的程序禁止状态的改变; 以及第二禁止信息控制电路，其基于相对于存储区域的第二禁止信息，禁止将程序禁止信息从允许状态改变为相对于存储区域的程序禁止状态的程序。

公开(公告)号：US07565477B2

公开(公告)日：2009-07-21

申请号：US11644031

申请日：2006-12-22

申请人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

发明人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

IPC分类号： G06F12/00

CPC分类号： G06F12/1433 ,  G06F2212/2022

摘要： A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.

摘要翻译： 半导体器件包括：包括非易失性存储单元的存储器区域; 禁用与存储器区域相对应的信息存储单元，每个禁用信息存储单元存储指示是否在每个对应的存储器区域中禁用或启用编程的第一程序禁用信息; 程序禁用信息选择电路，当根据集合程序禁止信息指示是否编程是否被编程时，输出第二程序禁用信息以禁止在对应的存储器区域中的编程，而不管第一程序禁用信息 在存储区域中集中禁止，程序禁止信息选择电路输出第一程序禁用信息作为编程时的第二程序禁用信息不被集中禁用; 以及程序控制电路，其根据第二程序禁止信息禁止或使得能够在对应的存储器区域中进行编程。

公开(公告)号：US20080155180A1

公开(公告)日：2008-06-26

申请号：US11644031

申请日：2006-12-22

申请人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

发明人： Kenji Shibata ,  Masahiko Okura ,  Kenta Kato ,  Mitsuhiro Nagao ,  Stewart Wang ,  Katherine Butler ,  Cheung Nga Tik

IPC分类号： G06F12/02

CPC分类号： G06F12/1433 ,  G06F2212/2022

摘要： A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.

摘要翻译： 半导体器件包括：包括非易失性存储单元的存储器区域; 禁用与存储器区域相对应的信息存储单元，每个禁用信息存储单元存储指示是否在每个对应的存储器区域中禁用或启用编程的第一程序禁用信息; 程序禁用信息选择电路，当根据集合程序禁止信息指示是否编程是否被编程时，输出第二程序禁用信息以禁止在对应的存储器区域中的编程，而不管第一程序禁用信息 在存储区域中集中禁止，程序禁止信息选择电路输出第一程序禁用信息作为编程时的第二程序禁用信息不被集中禁用; 以及程序控制电路，其根据第二程序禁止信息禁止或使得能够在对应的存储器区域中进行编程。

公开(公告)号：US5867438A

公开(公告)日：1999-02-02

申请号：US726168

申请日：1996-10-04

申请人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括读取或写入存储单元的数据的数据读/写电路，刷新存储在存储单元中的数据的自刷新电路，以及供给单元 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。