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    Semiconductor wafer
    1.
    发明授权
    Semiconductor wafer 失效
    半导体晶圆

    公开(公告)号：US5739546A

    公开(公告)日：1998-04-14

    申请号：US666646

    申请日：1996-06-18

    申请人： Mitsuhiro Saitou ,  Kouji Numazaki ,  Hiroyuki Ban

    发明人： Mitsuhiro Saitou ,  Kouji Numazaki ,  Hiroyuki Ban

    IPC分类号： H01L21/66 ,  H01L21/822 ,  H01L23/528 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10

    CPC分类号： H01L22/32 ,  H01L23/5286 ,  H01L27/0218 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.

    摘要翻译： 具有相对宽的电源线和接地线的半导体晶片，并且还可以防止这些线之间的短路。 多个集成电路形成区域已经形成集成电路，被布置在半导体晶片上。 在硅衬底上形成氧化硅膜，在氧化硅膜上形成接地线导体。 该接地线导体在划线上延伸。 在氧化硅膜上沉积由氧化硅膜构成的层绝缘膜，其间插入有接地线导体，并且在该层绝缘膜上形成与该接地线导体重叠的电源线导体。 电源线导体在划线上延伸。 在集成电路形成区域中，电源焊盘和电源线导体电连接。 接地焊盘和接地线导体也电连接。

    Semiconductor device having alignment mark
    5.
    发明授权
    Semiconductor device having alignment mark 失效
    具有对准标记的半导体器件

    公开(公告)号：US6081040A

    公开(公告)日：2000-06-27

    申请号：US39340

    申请日：1998-03-16

    申请人： Shoichi Okuda ,  Mitsuhiro Saitou ,  Hiroyuki Ban

    发明人： Shoichi Okuda ,  Mitsuhiro Saitou ,  Hiroyuki Ban

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/544 ,  H01L21/465

    CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002

    摘要： An alignment mark for determining a position of a thin film resistor formed on a semiconductor chip. The alignment mark is disposed on a capacitor formation region of the semiconductor chip. Because aluminum wiring members of the semiconductor chip are not disposed adjacent to the alignment mark within the capacitor formation region, the alignment mark can be precisely recognized. As a result, the position of the thin film resistor can be also precisely determined.

    摘要翻译： 用于确定形成在半导体芯片上的薄膜电阻器的位置的对准标记。 对准标记设置在半导体芯片的电容器形成区域上。 由于半导体芯片的铝布线构件不与电容器形成区域内的对准标记相邻配置，因此可以精确地识别对准标记。 结果，也可以精确地确定薄膜电阻器的位置。

    Semiconductor device and manufacturing method thereof
    6.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06242787B1

    公开(公告)日：2001-06-05

    申请号：US08748896

    申请日：1996-11-15

    申请人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

    发明人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

    IPC分类号： H01L2976

    CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

    摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

    摘要翻译： 一种包括减小表面场强度型LDMOS晶体管的半导体器件，其可以防止当向其漏极施加反向电压时在沟道形成部分处的元件的击穿。 在N型衬底中形成P阱和N阱以产生双阱结构，其中源极被设置为与N型衬底的电位相等。 N阱的漂移区域具有掺杂浓度以满足所谓的RESURF条件，其可以提供高的击穿电压低导通电阻。 当向漏极施加反向电压时，包括N阱，P阱和N型衬底的寄生双极晶体管形成朝向衬底的通电路径，使得元件在沟道形成时击穿 在施加反向电压时部分是可避免的。

    Load driving circuit with boosting timing control
    7.
    发明授权
    Load driving circuit with boosting timing control 失效
    负载驱动电路具有升压时序控制

    公开(公告)号：US6157246A

    公开(公告)日：2000-12-05

    申请号：US109732

    申请日：1998-07-02

    申请人： Mitsuhiro Saitou ,  Hiroyuki Ban

    发明人： Mitsuhiro Saitou ,  Hiroyuki Ban

    IPC分类号： B60R21/01 ,  G05F1/10

    CPC分类号： B60R21/017

    摘要： The present invention is aimed at avoiding noise generation accompanying switching actions in booster circuits for a load such as an air-bag driving circuit. In an air-bag driving circuit, which is designed to actuate an igniting transistor 13 in response to output of a collision detecting signal from a collision detector 7 for detecting a collision condition of a vehicle so as to supply an igniting current to a squib 11 based on a voltage boosted by booster circuits 4 and 5, the boosting operation of the booster circuits 4 and 5 is inhibited while the collision detecting signal is absent and started when the collision detecting signal is output from the collision detector 7.

    摘要翻译： 本发明旨在避免伴随诸如气囊驱动电路的负载的升压电路中的切换动作的噪声产生。 在气囊驱动电路中，其被设计成响应来自碰撞检测器7的碰撞检测信号的输出来致动点火晶体管13，用于检测车辆的碰撞状况，以便向点火器11提供点火电流 基于由升压电路4和5升压的电压，当碰撞检测信号从碰撞检测器7输出时，不存在冲突检测信号并开始升压电路4和5的升压操作。

    Reference voltage generating circuit having reduced current consumption with varying loads
    9.
    发明授权
    Reference voltage generating circuit having reduced current consumption with varying loads 失效
    参考电压发生电路具有随着负载变化而具有降低的电流消耗

    公开(公告)号：US5719522A

    公开(公告)日：1998-02-17

    申请号：US814935

    申请日：1997-03-12

    申请人： Mitsuhiro Saitou ,  Hajime Ito ,  Kiyoshi Yamamoto ,  Hiroyuki Ban

    发明人： Mitsuhiro Saitou ,  Hajime Ito ,  Kiyoshi Yamamoto ,  Hiroyuki Ban

    IPC分类号： G05F3/30 ,  G05F3/22 ,  G06F1/26 ,  G11C5/14 ,  G05F1/10

    CPC分类号： G05F3/222 ,  G11C5/147

    摘要： A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.

    摘要翻译： 可变负载电流供给单元将恒定电压输出单元消耗的电流供给到其电源端子，并通过基准电压输出端子向负载电路供给要消耗的电流。 恒定电压输出单元将电源端子的电位即基准电压输出端子的电位维持在固定电位。 基极电位控制单元将可变负载电流供给单元中的基准电压输出端子上的电位的变化负反馈到射极跟随器晶体管的基极。 以这种方式，当负载电流消耗的电流减小并且参考电压输出端子上的电位稍微增加时，可变负载电流供应单元提供的电流减小。

    Electronic circuit device
    10.
    发明授权
    Electronic circuit device 失效
    电子电路装置

    公开(公告)号：US5483217A

    公开(公告)日：1996-01-09

    申请号：US91718

    申请日：1993-07-15

    申请人： Takashi Nagasaka ,  Mitsuhiro Saitou ,  Takahisa Koyasu ,  Hiroyuki Ban ,  Yuji Otani ,  Kengo Oka ,  Kyoko Nagaoka

    发明人： Takashi Nagasaka ,  Mitsuhiro Saitou ,  Takahisa Koyasu ,  Hiroyuki Ban ,  Yuji Otani ,  Kengo Oka ,  Kyoko Nagaoka

    IPC分类号： H05K1/02 ,  H05K1/09 ,  H05K1/14 ,  H05K1/16 ,  H05K3/28 ,  H01C1/02

    CPC分类号： H05K3/284 ,  H05K1/167 ,  H05K1/0271 ,  H05K1/095 ,  H05K1/141 ,  H05K2201/0317 ,  H05K2201/09236 ,  H05K2201/10386 ,  H05K2201/10545

    摘要： An electronic circuit device decreases dispersion in the output of the circuit caused by changes in the resistance of the resistors resulting from stress. Resistor positions are selected on the circuit board so that a change in the circuit output caused by a change in resistance of a first resistor group becomes equal to a change caused by a change in resistance caused by a second resistor group, these changes being in opposite directions so as to cancel each other. Alternately, a plurality of resistors are connected to form a composite resistor such that the effect upon resistance of the composite resistor caused by the resistor having decreased resistance is cancelled by the effect upon resistance of the composite resistor caused by a resistor having an increased resistance.

    摘要翻译： 电子电路装置减少由于应力引起的电阻电阻变化引起的电路输出中的色散。 在电路板上选择电阻器位置，使得由第一电阻器组的电阻变化引起的电路输出的变化等于由第二电阻器组造成的电阻变化引起的变化，这些变化是相反的 方向相互抵消。 或者，连接多个电阻器以形成复合电阻器，使得由具有降低的电阻的电阻器引起的复合电阻器的电阻的影响由于由具有增加的电阻的电阻器引起的复合电阻器的电阻的影响而被抵消。