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公开(公告)号：US20120119356A1
公开(公告)日：2012-05-17
申请号：US13106333
申请日：2011-05-12
Applicant: Mitsuhisa WATANABE , Ichiro ANJOH
Inventor： Mitsuhisa WATANABE , Ichiro ANJOH
IPC: H01L23/498
CPC classification number: H01L21/561 , H01L21/6835 , H01L21/6836 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/544 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/90 , H01L24/94 , H01L2221/68327 , H01L2221/68381 , H01L2223/54486 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/1134 , H01L2224/13099 , H01L2224/1601 , H01L2224/16225 , H01L2224/16237 , H01L2224/274 , H01L2224/32225 , H01L2224/73204 , H01L2224/75 , H01L2224/81193 , H01L2224/83191 , H01L2224/83194 , H01L2224/83856 , H01L2224/90 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2924/3512 , H01L2924/00
Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.
Abstract translation: 半导体装置包括半导体芯片，其中多个电极焊盘设置在主表面上，并且多个凸起电极设置在半导体芯片的电极焊盘上。 半导体装置还包括布线基板，其分配在半导体芯片的主表面的一侧，并且位于半导体芯片的主表面的中心区域中，以与半导体芯片的边缘部分分离 芯片至少50μm以上。 半导体装置还包括设置在布线板上的多个外部端子，并且通过布线板的布线与多个凸起电极电连接，以及设置在半导体芯片和布线板之间的密封部 由底部填充材料制成，其覆盖凸起电极和布线之间的连接部分。
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2.发明申请
公开(公告)号：US20090184430A1
公开(公告)日：2009-07-23
申请号：US12349809
申请日：2009-01-07
Applicant: Mitsuhisa WATANABE , Ichiro ANJOH
Inventor： Mitsuhisa WATANABE , Ichiro ANJOH
IPC: H01L23/498
CPC classification number: H01L25/0657 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/06136 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/50 , H01L2224/73204 , H01L2224/73253 , H01L2224/73263 , H01L2224/73265 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2224/85
Abstract: Semiconductor device 1 includes: first wiring board 5 provided with a plurality of external terminals 9 on the under surface thereof; first semiconductor chip 3 with the under surface thereof mounted on the upper surface of first wiring board 5; and second semiconductor chip 10 with the under surface thereof mounted on the upper surface of first semiconductor chip 3. On the upper surface of first wiring board 5, connecting pad 6a and connecting pad 6b are provided, while connecting pad 6a is electrically connected with the under surface of first semiconductor chip 3 and connecting pad 6b is arranged closely to an end portion of first semiconductor chip 3. Connecting pad 6a and connecting pad 6b are electrically connected with external terminals 9. Semiconductor device 1 further includes: connecting pad 6c provided as contacting or as being close to an upper end portion of second semiconductor chip 10 while being electrically connected with the upper surface of second semiconductor chip 10, and wire 12 which electrically connects connecting pad 6b and connecting pad 6c.
Abstract translation: 半导体装置1包括：在其下表面上设置有多个外部端子9的第一布线板5; 第一半导体芯片3，其下表面安装在第一布线板5的上表面上; 并且其第二半导体芯片10的下表面安装在第一半导体芯片3的上表面上。在第一布线板5的上表面上设置有连接焊盘6a和连接焊盘6b，而连接焊盘6a与 第一半导体芯片3的下表面和连接焊盘6b靠近第一半导体芯片3的端部设置。连接焊盘6a和连接焊盘6b与外部端子9电连接。半导体装置1还包括：连接焊盘6c， 接触或接近第二半导体芯片10的上端部，同时与第二半导体芯片10的上表面电连接;以及导线12，其将连接焊盘6b和连接焊盘6c电连接。
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公开(公告)号：US20090020874A1
公开(公告)日：2009-01-22
申请号：US12175714
申请日：2008-07-18
Applicant: Mitsuhisa WATANABE , Ichiro ANJOH
Inventor： Mitsuhisa WATANABE , Ichiro ANJOH
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L24/06 , H01L21/563 , H01L21/6836 , H01L23/3114 , H01L23/49833 , H01L23/4985 , H01L24/83 , H01L24/90 , H01L25/0655 , H01L25/105 , H01L2221/68327 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/1134 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75743 , H01L2224/83191 , H01L2224/83194 , H01L2224/838 , H01L2224/83851 , H01L2225/1023 , H01L2225/107 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/19041 , H01L2924/30105 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.
Abstract translation: 根据本发明的半导体器件设置有半导体芯片，其中在主表面上设置多个电极焊盘，设置在半导体芯片的电极焊盘上的多个凸块电极，方形布线板， 设置在半导体芯片的主表面的一侧，并且其中彼此面对的外周的至少两侧位于半导体芯片的主表面上的区域中，多个外部端子是 设置在布线板上，并且通过布线板的布线电连接到多个凸块电极;以及密封材料，其设置在半导体芯片和布线板之间，并且覆盖凸块之间的连接部分 电极和接线。
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公开(公告)号：US20110092065A1
公开(公告)日：2011-04-21
申请号：US12976089
申请日：2010-12-22
Applicant: Eiji YOSHIDA , Takao OHNO , Yoshito AKUTAGAWA , Koji SAWAHATA , Masataka MIZUKOSHI , Takao NISHIMURA , Akira TAKASHIMA , Mitsuhisa WATANABE
Inventor： Eiji YOSHIDA , Takao OHNO , Yoshito AKUTAGAWA , Koji SAWAHATA , Masataka MIZUKOSHI , Takao NISHIMURA , Akira TAKASHIMA , Mitsuhisa WATANABE
IPC: H01L21/44
CPC classification number: H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/0401 , H01L2224/05572 , H01L2224/06181 , H01L2224/13008 , H01L2224/13009 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/45144 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0106 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
Abstract translation: 提供一种半导体器件，其形成具有彼此堆叠的半导体器件的三维半导体器件。 在该半导体器件中，在具有形成在外侧的主面上的集成电路单元和电极焊盘的硅半导体基板中形成有孔。 通过蚀刻形成孔，电极焊盘用作蚀刻停止层。 埋入电极形成在孔中。 该嵌入电极用于将电极焊盘导电到硅半导体衬底的底侧的主表面。
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5.发明申请SEMICONDUCTOR DEVICE PROVIDED WITH WIRE THAT ELECTRICALLY CONNECTS PRINTED WIRING BOARD AND SEMICONDUCTOR CHIP EACH OTHER 有权电连接器的电子设备电连接印刷电路板和半导体芯片每个其他
公开(公告)号：US20110006418A1
公开(公告)日：2011-01-13
申请号：US12830846
申请日：2010-07-06
Applicant: Mitsuhisa WATANABE , Keiyo KUSANAGI
Inventor： Mitsuhisa WATANABE , Keiyo KUSANAGI
IPC: H01L23/488 , H01L23/49
CPC classification number: H01L24/97 , H01L21/6836 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2221/68327 , H01L2224/05554 , H01L2224/06136 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4899 , H01L2224/4917 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/78301 , H01L2224/85001 , H01L2224/85007 , H01L2224/85051 , H01L2224/85186 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/8592 , H01L2224/85986 , H01L2224/97 , H01L2225/0651 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/20751 , H01L2924/30105 , H05K3/0052 , H05K3/328 , H05K2201/10477 , H05K2203/049 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/00012 , H01L2224/48132 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
Abstract: In one embodiment, a semiconductor device includes a printed wiring board provided with a connection pad, a semiconductor chip provided with an electrode pad and a conductive wire. One end of the conductive wire is connected to the connection pad of the printed wiring board and the other end of the conductive wire is connected to the electrode pad of the semiconductor chip. The semiconductor chip is mounted on the printed wiring board so that the first surface of the semiconductor chip provided with the electrode pad is oriented opposite to the printed wiring board. A first insulating layer is formed on the first surface of the semiconductor chip oriented opposite to the printed wiring board. A thermoplastic second insulating layer is formed on the first insulating layer. Part of the conductive wire between one end and the other end is buried in the second insulating layer.
Abstract translation: 在一个实施例中，半导体器件包括设置有连接焊盘的印刷线路板，设置有电极焊盘和导线的半导体芯片。 导电线的一端连接到印刷电路板的连接焊盘，导电线的另一端连接到半导体芯片的电极焊盘。 半导体芯片安装在印刷线路板上，使得设置有电极焊盘的半导体芯片的第一表面与印刷线路板相对。 第一绝缘层形成在与印刷线路板相对定向的半导体芯片的第一表面上。 在第一绝缘层上形成热塑性第二绝缘层。 一端和另一端之间的导线的一部分被埋在第二绝缘层中。
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公开(公告)号：US20100295167A1
公开(公告)日：2010-11-25
申请号：US12784170
申请日：2010-05-20
Applicant: Mitsuhisa WATANABE
Inventor： Mitsuhisa WATANABE
IPC: H01L23/488
CPC classification number: H01L24/97 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/07802 , H01L2924/13091 , H01L2924/15311 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00
Abstract: A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.
Abstract translation: 半导体器件包括绝缘基板，半导体芯片，绝缘层和密封层。 绝缘基板具有开口。 半导体芯片设置在开口中。 绝缘层设置在绝缘基板的第一表面上。 绝缘层覆盖开口。 密封层设置在绝缘基板的第二表面上。 密封层密封半导体芯片和开口。
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7.发明申请
公开(公告)号：US20090014874A1
公开(公告)日：2009-01-15
申请号：US12169072
申请日：2008-07-08
Applicant: Mitsuhisa WATANABE , Ichiro ANJO
Inventor： Mitsuhisa WATANABE , Ichiro ANJO
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L21/6836 , H01L21/563 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/06 , H01L24/81 , H01L24/83 , H01L24/86 , H01L24/90 , H01L24/97 , H01L2221/68327 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/1134 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/75743 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2224/838 , H01L2224/83851 , H01L2224/97 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/181 , H01L2224/81 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor apparatus includes a semiconductor chip, a wired board, a plurality of bump electrodes, a plurality of external terminals, and insulating material. The semiconductor chip includes a plurality of electrode pads arranged in a central area on one surface. The wired board is arranged as facing one surface of the semiconductor chip, and includes a wiring. The bump electrode is provided between surfaces at which the semiconductor chip and the wired board face each other, and electrically connects the electrode pad and the wiring. The external terminal corresponds to a plurality of bump electrodes, and is mounted on the wired board. The insulating material is provided between the semiconductor chip and the wired board, and covers at least a connection part between the bump electrode and the wiring. The wiring of the wired board is configured to run in a straight line from a bump electrode-mounted position in a semiconductor chip-mounted surface of the wired board, to an external terminal-mounted surface of the wired board, and also, electrically connect the bump electrode and the corresponding external terminal.
Abstract translation: 半导体装置包括半导体芯片，布线板，多个凸块电极，多个外部端子和绝缘材料。 半导体芯片包括布置在一个表面上的中心区域中的多个电极焊盘。 布线板被布置为面对半导体芯片的一个表面，并且包括布线。 凸起电极设置在半导体芯片和布线板彼此面对的表面之间，并且电连接电极焊盘和布线。 外部端子对应于多个凸起电极，并且安装在布线板上。 绝缘材料设置在半导体芯片和布线板之间，并且至少覆盖凸起电极和布线之间的连接部分。 布线基板的布线被配置为从布线板的半导体芯片安装表面中的突起电极安装位置到布线板的外部端子安装表面的直线运行，并且还电连接 凸起电极和相应的外部端子。
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公开(公告)号：US20120118939A1
公开(公告)日：2012-05-17
申请号：US13295581
申请日：2011-11-14
Applicant: Keiyo KUSANAGI , Koichi HATAKEYAMA , Mitsuhisa WATANABE , Yusuke NAKANOYA , Hidenori MATSUSHITA , Toru MEURA , Kenzou MAEJIMA , Hiroki NIKAIDO , Mina NIKAIDO
Inventor： Keiyo KUSANAGI , Koichi HATAKEYAMA , Mitsuhisa WATANABE , Yusuke NAKANOYA , Hidenori MATSUSHITA , Toru MEURA , Kenzou MAEJIMA , Hiroki NIKAIDO , Mina NIKAIDO
CPC classification number: B23K1/0016 , H01L24/13 , H01L24/29 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/73204 , H01L2224/75251 , H01L2224/75252 , H01L2224/81193 , H01L2224/81203 , H01L2224/81209 , H01L2224/81815 , H01L2224/83192 , H01L2224/83203 , H01L2224/83862 , H01L2224/92125 , H01L2224/97 , H01L2924/00013 , H01L2924/01029 , H01L2924/15787 , H01L2924/181 , H05K3/3436 , H05K3/3489 , H05K2201/10674 , H05K2201/10977 , H05K2203/068 , H05K2203/1189 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2924/00
Abstract: The process for manufacturing the semiconductor device and the apparatus, which achieve stable production of semiconductor devices with improved connection reliability, is presented. First terminals of circuit boards 1 are arranged to face the corresponding bumps of semiconductor chips 2, respectively, and the resin layer 3 is disposed between the respective first terminals and the respective bumps to form laminates, and the laminates are simultaneously compressed from a direction of lamination, while heating a plurality of laminates. In such case, the diaphragm 54 disposed in a heating furnace 51 is abutted against a plurality of laminates or a member 531 to elastically deform the members while a plurality of laminates is heated in the heating furnace 51, so that laminates are simultaneously compressed from a direction of lamination, while heating thereof in a vacuum.
Abstract translation: 本发明提供了制造半导体器件的方法以及实现稳定生产具有改进的连接可靠性的半导体器件的装置。 电路板1的第一端子被分别布置成与半导体芯片2的相应凸块相对，并且树脂层3设置在相应的第一端子和相应的凸块之间以形成层压体，并且层叠体同时从 同时加热多个层压板。 在这种情况下，设置在加热炉51中的隔膜54抵靠多个层压体或构件531，以在加热炉51中加热多个层压体的同时使构件弹性变形，使得层压体同时从 层叠方向，同时在真空中加热。
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公开(公告)号：US20100301468A1
公开(公告)日：2010-12-02
申请号：US12787770
申请日：2010-05-26
Applicant: Mitsuhisa WATANABE , Keiyo Kusanagi , Koichi Hatakeyama , Hiroyuki Fujishima
Inventor： Mitsuhisa WATANABE , Keiyo Kusanagi , Koichi Hatakeyama , Hiroyuki Fujishima
CPC classification number: H01L23/16 , H01L21/4846 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/04042 , H01L2224/05554 , H01L2224/16235 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/83194 , H01L2224/8385 , H01L2224/83907 , H01L2224/85 , H01L2224/9202 , H01L2224/92144 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10161 , H01L2924/10162 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/81 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/0401 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device may include, but is not limited to a wiring board, a first insulator, a semiconductor chip, and a second insulator. The first insulator penetrates the wiring board. A top end of the first insulator is higher in level than an upper surface of the wiring board. The semiconductor chip is disposed on the top end of the first insulator. The semiconductor chip is separated from the upper surface of the wiring board. The second insulator covers the semiconductor chip and the upper surface of the wiring board.
Abstract translation: 半导体器件可以包括但不限于布线板，第一绝缘体，半导体芯片和第二绝缘体。 第一绝缘体穿透布线板。 第一绝缘体的顶端的电平高于布线板的上表面。 半导体芯片设置在第一绝缘体的顶端。 半导体芯片与布线板的上表面分离。 第二绝缘体覆盖半导体芯片和布线板的上表面。
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公开(公告)号：US20100252923A1
公开(公告)日：2010-10-07
申请号：US12726853
申请日：2010-03-18
Applicant: Mitsuhisa WATANABE , Keiyo Kusanagi , Koichi Hatakeyama
Inventor： Mitsuhisa WATANABE , Keiyo Kusanagi , Koichi Hatakeyama
IPC: H01L23/498 , H01L21/56
CPC classification number: H01L23/13 , H01L23/3128 , H01L23/315 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8592 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/1461 , H01L2924/15151 , H01L2924/15183 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device of the present invention includes a semiconductor chip formed with an electrode pad on a front side thereof, a wiring board having a wiring pattern, the wiring board having a front side opposing the back side of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the back side of the wiring board for electrical connection with the electrode pad through the wire and the wiring pattern, and a sealant for fixing the semiconductor chip on the front side of the wiring board so as to form a hollow which is continuous to a portion straddling the entirety of the back side of the semiconductor chip and the front side of the wiring board, and continuous to a portion adjacent to at least one outer peripheral surface of the semiconductor chip except for the back side of the same. The wiring board includes a throughhole in communication with the hollow.
Abstract translation: 本发明的半导体器件包括在其前侧形成有电极焊盘的半导体芯片，具有布线图案的布线板，所述布线板具有与半导体芯片的背面相对的正面，用于电 将半导体芯片的电极焊盘与布线板的布线图形连接，布置在布线板背面的外部端子，用于通过导线和布线图案与电极焊盘电连接;以及密封剂，用于固定 半导体芯片，以形成与跨越半导体芯片的背面和布线板的前侧的部分相连的部分连续的中空部分，并且连续于邻近于该部分的部分 半导体芯片除了背面以外的至少一个外周面。 布线板包括与中空部连通的通孔。
