公开(公告)号：US06879533B2

公开(公告)日：2005-04-12

申请号：US10609071

申请日：2003-06-27

申请人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

发明人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： An integrated circuit memory device can include a memory cell array having a plurality of memory cells, and a bit line sense amplifier configured to amplify data on a pair of bit lines from a memory cell of the memory cell array and to provide the amplified data on a data line and a complementary data line. An active load circuit includes a first load device electrically connected between the data line and a voltage source wherein an electrical resistance of the first load device is varied responsive to a voltage level of the data line. The active load circuit also includes a second load device electrically connected between the complementary data line and the voltage source wherein an electrical resistance of the second load device is varied responsive to a voltage level of the complementary data line. Related methods are also discussed.

摘要翻译： 集成电路存储器件可以包括具有多个存储单元的存储单元阵列和位线读出放大器，该位线读出放大器被配置为放大来自存储单元阵列的存储单元的一对位线上的数据，并将放大数据提供到 数据线和补充数据线。 有源负载电路包括电连接在数据线和电压源之间的第一负载装置，其中第一负载装置的电阻响应于数据线的电压电平而变化。 有源负载电路还包括电连接在互补数据线和电压源之间的第二负载装置，其中第二负载装置的电阻响应补充数据线的电压电平而变化。 还讨论了相关方法。

公开(公告)号：US06777987B2

公开(公告)日：2004-08-17

申请号：US10394682

申请日：2003-03-21

申请人： Moo-sung Chae ,  Chi-wook Kim ,  Sung-min Seo

发明人： Moo-sung Chae ,  Chi-wook Kim ,  Sung-min Seo

IPC分类号： H03K300

CPC分类号： H03K5/14 ,  H03K5/12 ,  H03K19/01721 ,  H04L25/0288

摘要： A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal. The first signal buffer has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal. The second signal buffer has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to the node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.

摘要翻译： 信号线驱动电路包括反相缓冲器，脉冲发生器，第一信号缓冲器和第二信号缓冲器。 这里，反相缓冲器接收输入信号，并包括连接到信号线的输出端以驱动信号线。 脉冲发生器接收输入信号以产生脉冲信号。 第一信号缓冲器具有连接到脉冲发生器的输出端子的控制端子和连接到信号线的节点的输入/输出端子。 第一信号缓冲器响应于第一控制信号减小在信号线上传播的信号的上升转变时间。 第二信号缓冲器具有连接到脉冲发生器的输出端的控制端子和连接到信号线的节点的输入/输出端子。 第二信号缓冲器响应于第一控制信号减少在信号线上传播的信号的下降转变时间。

公开(公告)号：US06795372B2

公开(公告)日：2004-09-21

申请号：US10389482

申请日：2003-03-14

申请人： Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

发明人： Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

IPC分类号： G11C800

CPC分类号： G11C7/18 ,  G11C7/065 ,  G11C2207/065

摘要： Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

摘要翻译： 用于同步DRAM的位线读出放大器驱动控制电路和方法选择性地供给和暂停供给位线读出放大器的工作电压。 更具体地，同步DRAM包括存储单元阵列，该存储单元阵列至少包括根据列地址划分的第一列块和第二列块，第一位线读出放大器被配置为感测从第一列块输出的数据 以及被配置为感测从存储单元阵列的第二列块输出的数据的第二位线读出放大器。 位线读出放大器驱动控制电路或方法响应于行地址选择信号，向第一和第二位线读出放大器提供工作电压，并响应列选择信号，该列选择信号选择第一位 列块，以暂停向第二位线读出放大器提供工作电压。

公开(公告)号：US06815989B2

公开(公告)日：2004-11-09

申请号：US10325766

申请日：2002-12-19

申请人： Sung-min Seo

发明人： Sung-min Seo

IPC分类号： H03L706

CPC分类号： H03H11/26

摘要： Delay line circuits and methods include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding unit delay cell is connected to an input of a succeeding unit delay cell. At least two of the unit delay cells in the series are sequentially activated in response to an activation signal. The sequential activation may be performed by a control circuit that is connected to the series of unit delay cells.

摘要翻译： 延迟线电路和方法包括一系列单元延迟单元，其中相应的单元延迟单元包括顺序连接的输入和输出，使得前一单元延迟单元的输出连接到后续单元延迟单元的输入。 串联中的至少两个单元延迟单元响应于激活信号被顺序地激活。 顺序激活可以由连接到一系列单位延迟单元的控制电路来执行。

公开(公告)号：US20050111273A1

公开(公告)日：2005-05-26

申请号：US10884723

申请日：2004-07-02

申请人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

发明人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

IPC分类号： G11C7/00 ,  G11C5/00 ,  G11C7/10

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066

摘要： Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits. When the number of processed data bits is n, the control signal is set to a first level and the inverted control signal is set to a second level, and when the number of processed data bits is k, the control signal is set to a second level and the inverted control signal is set to a first level. Since the buffer circuit and the memory system selectively output the data strobe signal according to the number of data bits, a point of time when the data are latched can be advanced and a setup/hold time of the data can be reduced.

摘要翻译： 提供了一种用于根据数据位数选择性地输出数据选通信号的缓冲电路和存储系统。 缓冲电路包括第一缓冲单元，第二缓冲单元和第三缓冲单元。 第一缓冲器单元放大并输出第一信号。 第二缓冲器单元放大并输出第二信号，或者根据控制信号的逻辑电平输出第一信号。 第三缓冲器单元根据反相控制信号的逻辑电平放大第一信号以发送或不发送放大的第一信号到第二缓冲器单元。 控制信号和反相控制信号的逻辑电平根据处理的数据位的数量来确定。 当处理数据位数为n时，将控制信号设置为第一电平，将反相控制信号设置为第二电平，当处理数据位数为k时，将控制信号设置为第二电平 电平，并且反相控制信号被设置为第一电平。 由于缓冲电路和存储器系统根据数据位数选择性地输出数据选通信号，所以可以提前数据锁存的时间点，并且可以减少数据的建立/保持时间。

公开(公告)号：US07038972B2

公开(公告)日：2006-05-02

申请号：US10793209

申请日：2004-03-04

申请人： Sung-min Seo ,  Chi-wook Kim ,  Kyu-hyoun Kim

发明人： Sung-min Seo ,  Chi-wook Kim ,  Kyu-hyoun Kim

IPC分类号： G01C8/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

摘要： A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in synchronization with the output clock signal output from the clock signal control unit; and the output control unit receives the output clock signal output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.

摘要翻译： 提供了一种双倍数据速率（“DDR”）同步动态随机存取存储器（“SDRAM”）半导体器件，其防止当将数据写入DDR SDRAM半导体器件时从数据读取和写入DDR SDRAM半导体器件的数据之间的冲突 ，其包括延迟锁定环（“DLL”）电路，时钟信号控制单元，输出单元和输出控制单元，其中DLL电路补偿输入时钟信号的偏斜并产生输出时钟信号; 当读出存储在DDR SDRAM半导体器件中的数据时，时钟信号控制单元接收到激活的读取信号，当DLL电路对输入时钟信号执行锁定操作时激活的DLL锁定信号和输出时钟信号，并且输出 当读取信号或DLL锁定信号有效时，输出时钟信号; 输出单元缓冲存储在DDR SDRAM半导体器件中的数据，并将数据与从时钟信号控制单元输出的输出时钟信号同步地输出到DDR SDRAM半导体器件的外部; 并且输出控制单元接收从时钟信号控制单元输出的输出时钟信号和读取信号，并将读出的信号与从时钟信号控制单元输出的输出时钟信号同步输出到输出单元。

公开(公告)号：US07269078B2

公开(公告)日：2007-09-11

申请号：US11443736

申请日：2006-05-31

申请人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

发明人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

IPC分类号： G11C7/10

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066

摘要： Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits. When the number of processed data bits is n, the control signal is set to a first level and the inverted control signal is set to a second level, and when the number of processed data bits is k, the control signal is set to a second level and the inverted control signal is set to a first level. Since the buffer circuit and the memory system selectively output the data strobe signal according to the number of data bits, a point of time when the data are latched can be advanced and a setup/hold time of the data can be reduced.

摘要翻译： 提供了一种用于根据数据位数选择性地输出数据选通信号的缓冲电路和存储系统。 缓冲电路包括第一缓冲单元，第二缓冲单元和第三缓冲单元。 第一缓冲器单元放大并输出第一信号。 第二缓冲器单元放大并输出第二信号，或者根据控制信号的逻辑电平输出第一信号。 第三缓冲器单元根据反相控制信号的逻辑电平放大第一信号以发送或不发送放大的第一信号到第二缓冲器单元。 控制信号和反相控制信号的逻辑电平根据处理的数据位的数量来确定。 当处理数据位数为n时，将控制信号设置为第一电平，将反相控制信号设置为第二电平，当处理数据位数为k时，将控制信号设置为第二电平 电平，并且反相控制信号被设置为第一电平。 由于缓冲电路和存储器系统根据数据位数选择性地输出数据选通信号，所以可以提前数据锁存的时间点，并且可以减少数据的建立/保持时间。

公开(公告)号：US07123520B2

公开(公告)日：2006-10-17

申请号：US10884723

申请日：2004-07-02

申请人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

发明人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

IPC分类号： G11C16/10

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066

摘要： Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits. When the number of processed data bits is n, the control signal is set to a first level and the inverted control signal is set to a second level, and when the number of processed data bits is k, the control signal is set to a second level and the inverted control signal is set to a first level. Since the buffer circuit and the memory system selectively output the data strobe signal according to the number of data bits, a point of time when the data are latched can be advanced and a setup/hold time of the data can be reduced.

公开(公告)号：US20060215462A1

公开(公告)日：2006-09-28

申请号：US11443736

申请日：2006-05-31

申请人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

发明人： Sung-min Seo ,  Chul-soo Kim ,  Kyu-hyoun Kim ,  Jin-kyoung Jung

IPC分类号： G11C7/10

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066

摘要： Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits. When the number of processed data bits is n, the control signal is set to a first level and the inverted control signal is set to a second level, and when the number of processed data bits is k, the control signal is set to a second level and the inverted control signal is set to a first level. Since the buffer circuit and the memory system selectively output the data strobe signal according to the number of data bits, a point of time when the data are latched can be advanced and a setup/hold time of the data can be reduced.

摘要翻译： 提供了一种用于根据数据位数选择性地输出数据选通信号的缓冲电路和存储系统。 缓冲电路包括第一缓冲单元，第二缓冲单元和第三缓冲单元。 第一缓冲器单元放大并输出第一信号。 第二缓冲器单元放大并输出第二信号，或者根据控制信号的逻辑电平输出第一信号。 第三缓冲器单元根据反相控制信号的逻辑电平放大第一信号以发送或不发送放大的第一信号到第二缓冲器单元。 控制信号和反相控制信号的逻辑电平根据处理的数据位的数量来确定。 当处理数据位数为n时，将控制信号设置为第一电平，将反相控制信号设置为第二电平，当处理数据位数为k时，将控制信号设置为第二电平 电平，并且反相控制信号被设置为第一电平。 由于缓冲电路和存储器系统根据数据位数选择性地输出数据选通信号，所以可以提前数据锁存的时间点，并且可以减少数据的建立/保持时间。