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公开(公告)号:US4868853A
公开(公告)日:1989-09-19
申请号:US181528
申请日:1988-04-14
申请人: Morishi Izumita , Seiichi Mita , Nobukazu Doi , Masuo Umemoto , Hiroto Yamauchi , Shigeaki Fujino , Nobuo Murata
发明人: Morishi Izumita , Seiichi Mita , Nobukazu Doi , Masuo Umemoto , Hiroto Yamauchi , Shigeaki Fujino , Nobuo Murata
IPC分类号: H03M5/14
摘要: A demodulation circuit for demodulating a modulated digital including a unit for detecting a specific pattern contained in a series of data before modulation, a unit for judging the phase relation between the specific pattern and a clock pulse used for demodulation, a unit for performing a counting operation on the basis of the result of said judgment, and a unit for controlling the phase of said clock pulse for demodulation on the basis of the count.
摘要翻译: 一种用于解调调制数字的解调电路,包括用于检测包含在调制之前的一系列数据中的特定模式的单元,用于判断特定模式与用于解调的时钟脉冲之间的相位关系的单元,用于执行计数的单元 基于所述判断结果的操作,以及用于基于计数控制用于解调的所述时钟脉冲的相位的单元。