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公开(公告)号：US07103127B2
公开(公告)日：2006-09-05
申请号：US09823316
申请日：2001-03-30
CPC分类号： H03L7/099 , H03B2201/025 , H03B2201/0291 , H03J2200/10 , H03L5/00 , H03L7/087 , H03L7/113
摘要： Systems for controlling the frequency of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system comprises a controllable oscillator and a frequency control circuit. The controllable oscillator is configured to generate an output signal that has a predefined frequency. The controllable oscillator is also configured with a plurality of operational states that are controlled by the frequency control circuit. Each operational state of the controllable oscillator defines a distinct frequency for the output signal of the controllable oscillator. The frequency control circuit receives the output signal of the controllable oscillator and determines the distinct frequency for the output signal that best approximates the predefined frequency. The frequency control circuit may also provide a control signal to the controllable oscillator that is configured to change the controllable oscillator to the operational state corresponding to the distinct frequency that best approximates the predefined frequency.
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公开(公告)号：US06744328B2
公开(公告)日：2004-06-01
申请号：US10210698
申请日：2002-07-31
申请人： Rahul Magoon , Alyosha C. Molnar , Jeff Zachan
发明人： Rahul Magoon , Alyosha C. Molnar , Jeff Zachan
IPC分类号： H03B100
摘要： Systems for controlling the amplitude of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system provides a circuit having a controllable oscillator and an amplitude control circuit. The controllable oscillator is configured to generate an output signal having a predefined frequency and a predefined amplitude. The controllable oscillator is also configured with a plurality of operational states that are controlled by the amplitude control circuit. Each operational state of the controllable oscillator defines a particular current bias associated with a distinct amplitude of the output signal of the controllable oscillator. The amplitude control circuit receives the output signal of the controllable oscillator and determines the amplitude. When the amplitude of the output signal of the controllable oscillator is less than the predefined amplitude, the amplitude control circuit provides a control signal to the controllable oscillator. The control signal is configured to change the controllable oscillator to the operational state corresponding to the distinct amplitude that best approximates the predefined amplitude.
摘要翻译： 提供了用于控制频率合成器中的可控振荡器的输出信号的振幅的系统。 一种这样的系统提供具有可控振荡器和振幅控制电路的电路。 可控振荡器被配置为产生具有预定义频率和预定幅度的输出信号。 可控振荡器还配置有由幅度控制电路控制的多个操作状态。 可控振荡器的每个操作状态定义与可控振荡器的输出信号的不同幅度相关联的特定电流偏置。 振幅控制电路接收可控振荡器的输出信号并确定振幅。 当可控振荡器的输出信号的振幅小于预定幅度时，振幅控制电路向可控振荡器提供控制信号。 控制信号被配置为将可控振荡器改变到对应于最接近于预定幅度的不同幅度的操作状态。
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3.发明授权System for improving the parasitic resistance and capacitance effect of a transistor-based switch 有权用于提高基于晶体管的开关的寄生电阻和电容效应的系统公开(公告)号：US06734713B1
公开(公告)日：2004-05-11
申请号：US09823679
申请日：2001-03-30
申请人： Rahul Magoon , Alyosha C. Molnar , Jeff Zachan
发明人： Rahul Magoon , Alyosha C. Molnar , Jeff Zachan
IPC分类号： H03K1716
CPC分类号： H03K17/16
摘要： Systems for reducing the parasitic effects of a transistor-based switch are provided. In one such system provides a transistor circuit for implementing a switch having reduced parasitic effects. In general, the transistor circuit comprises a first switch node, a second switch node, a third switch node, a transistor device, and a circuit configured to reduce the parasitic characteristics of the transistor device. The first switch node is for connecting to one node of an external circuit. The second switch node is for connecting to a second node of an external circuit. The transistor device is a three-terminal device. The first terminal is connected to the first switch node. The second terminal is connected to the second switch node. The third terminal is for receiving a control signal that operates the transistor circuit as a switch by controlling the electrical connectivity between the first terminal and the second terminal. The third switch node is for receiving the control signal. The transistor circuit may also comprise an inverter circuit that is connected to the second terminal of the transistor device and is configured to provide a voltage to the second terminal when the control signal engages the transistor device.
摘要翻译： 提供了用于降低基于晶体管的开关的寄生效应的系统。 在一个这样的系统中，提供了用于实现具有减小的寄生效应的开关的晶体管电路。 通常，晶体管电路包括第一开关节点，第二开关节点，第三开关节点，晶体管器件和被配置为减小晶体管器件的寄生特性的电路。 第一个开关节点用于连接外部电路的一个节点。 第二开关节点用于连接到外部电路的第二节点。 晶体管器件是三端子器件。 第一个终端连接到第一个交换节点。 第二终端连接到第二交换节点。 第三端子用于通过控制第一端子和第二端子之间的电连接来接收操作晶体管电路作为开关的控制信号。 第三开关节点用于接收控制信号。 晶体管电路还可以包括逆变器电路，其连接到晶体管器件的第二端子，并且被配置为当控制信号接合晶体管器件时向第二端子提供电压。
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公开(公告)号：US06483391B1
公开(公告)日：2002-11-19
申请号：US09823285
申请日：2001-03-30
申请人： Rahul Magoon , Alyosha C. Molnar , Jeff Zachan
发明人： Rahul Magoon , Alyosha C. Molnar , Jeff Zachan
IPC分类号： H03L500
摘要： Systems for controlling the amplitude of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system provides a circuit having a controllable oscillator and an amplitude control circuit. The controllable oscillator is configured to generate an output signal having a predefined frequency and a predefined amplitude. The controllable oscillator is also configured with a plurality of operational states that are controlled by the amplitude control circuit. Each operational state of the controllable oscillator defines a particular current bias associated with a distinct amplitude of the output signal of the controllable oscillator. The amplitude control circuit receives the output signal of the controllable oscillator and determines the amplitude. When the amplitude of the output signal of the controllable oscillator is less than the predefined amplitude, the amplitude control circuit provides a control signal to the controllable oscillator. The control signal is configured to change the controllable oscillator to the operational state corresponding to the distinct amplitude that best approximates the predefined amplitude.
摘要翻译： 提供了用于控制频率合成器中的可控振荡器的输出信号的振幅的系统。 一种这样的系统提供具有可控振荡器和振幅控制电路的电路。 可控振荡器被配置为产生具有预定义频率和预定幅度的输出信号。 可控振荡器还配置有由幅度控制电路控制的多个操作状态。 可控振荡器的每个操作状态定义与可控振荡器的输出信号的不同幅度相关联的特定电流偏置。 振幅控制电路接收可控振荡器的输出信号并确定振幅。 当可控振荡器的输出信号的振幅小于预定幅度时，振幅控制电路向可控振荡器提供控制信号。 控制信号被配置为将可控振荡器改变到对应于最接近于预定幅度的不同幅度的操作状态。
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5.发明申请Method for modulating phase or frequency in a communication system using clock division 有权在使用时钟分频的通信系统中调制相位或频率的方法公开(公告)号：US20070024382A1
公开(公告)日：2007-02-01
申请号：US11440343
申请日：2006-05-24
申请人： Jeff Zachan , David Hartman , Ming Lin , Morten Damgaard , Scott Kee
发明人： Jeff Zachan , David Hartman , Ming Lin , Morten Damgaard , Scott Kee
IPC分类号： H03L7/00
CPC分类号： H04L27/2092 , H03C3/0933 , H03C3/0966 , H03C3/0983 , H03L7/1976 , H03L2207/12 , H04L27/2017 , H04L27/2046
摘要： A direct division modulator is provided. The direct division modulator includes a symbol mapper converting the input data from a binary bitstream to a desired frequency deviation, such as where the frequency deviation data encodes the information from the bitstream. A converter generates a divide value using the desired frequency deviation information, and a summer adds an average value to the divide value. A converter quantizes the divide value and shapes quantization noise associated with the quantized divide value. A divider modulates a reference signal with the quantized divide value and generates an output signal.
摘要翻译： 提供了直接分频调制器。 直接分频调制器包括将输入数据从二进制比特流转换为期望的频率偏差的符号映射器，例如频率偏差数据对来自比特流的信息进行编码的地方。 A转换器使用期望的频率偏差信息产生除法值，并且加法器将平均值加到除法值。 A转换器对分频值进行量化，并形成与量化除法相关联的量化噪声。 分频器用量化除法器调制参考信号并产生输出信号。
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6.发明授权Method for modulating phase or frequency in a communication system using clock division 有权在使用时钟分频的通信系统中调制相位或频率的方法公开(公告)号：US07417514B2
公开(公告)日：2008-08-26
申请号：US11440343
申请日：2006-05-24
申请人： Jeff Zachan , David Hartman , Ming Lin , Morten Damgaard , Scott Kee
发明人： Jeff Zachan , David Hartman , Ming Lin , Morten Damgaard , Scott Kee
IPC分类号： H03C3/06
CPC分类号： H04L27/2092 , H03C3/0933 , H03C3/0966 , H03C3/0983 , H03L7/1976 , H03L2207/12 , H04L27/2017 , H04L27/2046
摘要： A direct division modulator is provided. The direct division modulator includes a symbol mapper converting the input data from a binary bitstream to a desired frequency deviation, such as where the frequency deviation data encodes the information from the bitstream. A converter generates a divide value using the desired frequency deviation information, and a summer adds an average value to the divide value. A converter quantizes the divide value and shapes quantization noise associated with the quantized divide value. A divider modulates a reference signal with the quantized divide value and generates an output signal.
摘要翻译： 提供了直接分频调制器。 直接分频调制器包括将输入数据从二进制比特流转换为期望的频率偏差的符号映射器，例如频率偏差数据对来自比特流的信息进行编码的地方。 A转换器使用期望的频率偏差信息产生除法值，并且加法器将平均值加到除法值。 A转换器对分频值进行量化，并形成与量化除法相关联的量化噪声。 分频器用量化除法器调制参考信号并产生输出信号。
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