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    Process, voltage, temperature independent switched delay compensation scheme
    1.
    发明授权
    Process, voltage, temperature independent switched delay compensation scheme 有权
    过程，电压，温度独立的开关延迟补偿方案

    公开(公告)号：US08897411B2

    公开(公告)日：2014-11-25

    申请号：US13741994

    申请日：2013-01-15

    Applicant: Mosaid Technologies Incorporated

    Inventor： Gurpreet Bhullar ,  Graham Allan

    IPC: H03D3/24

    CPC classification number: H03L7/06 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089 ,  H03L7/093

    Abstract: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

    Abstract translation: 一种用于延迟锁定环路的延迟补偿电路，其包括具有精细延迟线的主延迟线，该延迟线包括精细延迟元件和包括粗延迟元件的粗延迟线，该主延迟线由控制器控制，该延迟补偿电路包括： 用于对粗略延迟元件进行建模的可调精细延迟，用于将可调节精细延迟控制为与粗略延迟元件基本相同的值的计数器，用于将系统时钟的表示应用于延迟补偿电路的电路 以及从计数器向控制器施加精细延迟计数的电路，用于将主延迟线的精细延迟线调整为与主延迟线的粗略延迟元件基本相同的值。

    Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory
    3.
    发明申请
    Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory 失效
    延迟锁定环路在同步动态随机存取存储器中的实现

    公开(公告)号：US20130121096A1

    公开(公告)日：2013-05-16

    申请号：US13732791

    申请日：2013-01-02

    Applicant: MOSAID Technologies Incorporated

    Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

    IPC: G11C7/22

    CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

    Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

    Clock mode determination in a memory system
    5.
    发明授权
    Clock mode determination in a memory system 有权

    公开(公告)号：US11347396B2

    公开(公告)日：2022-05-31

    申请号：US16950204

    申请日：2020-11-17

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00 ,  H03K5/00

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    Delay locked loop implementation in a synchronous dynamic random access memory
    6.
    发明授权
    Delay locked loop implementation in a synchronous dynamic random access memory 失效
    在同步动态随机存取存储器中延迟锁定环路的实现

    公开(公告)号：US08638638B2

    公开(公告)日：2014-01-28

    申请号：US13732791

    申请日：2013-01-02

    Applicant: MOSAID Technologies Incorporated

    Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

    IPC: G11C8/00

    CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

    Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

    Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
    8.
    发明申请
    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权

    公开(公告)号：US20230046725A1

    公开(公告)日：2023-02-16

    申请号：US17731408

    申请日：2022-04-28

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. Gillingham ,  Graham Allan

    IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

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