公开(公告)号：US20090039336A1

公开(公告)日：2009-02-12

申请号：US12176606

申请日：2008-07-21

申请人： Motoyasu Terao ,  Yoshitaka Sasago ,  Kenzo Kurotsuchi ,  Kazuo Ono ,  Yoshihisa Fujisaki ,  Norikatsu Takaura ,  Riichiro Takemura

发明人： Motoyasu Terao ,  Yoshitaka Sasago ,  Kenzo Kurotsuchi ,  Kazuo Ono ,  Yoshihisa Fujisaki ,  Norikatsu Takaura ,  Riichiro Takemura

IPC分类号： H01L45/00

CPC分类号： G11C11/5614 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/142 ,  H01L45/1675

摘要： The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen.

摘要翻译： 提高了能够存储信息的半导体装置的性能。 存储元件的存储层由底部电极侧的第一层和顶部电极侧的第二层形成。 第一层含有20-70原子％的Cu，Ag，Au，Al，Zn和Cd的第一元素基团的至少一种元素，含有3-40原子％的至少一种元素的第二元素基团 V，Nb，Ta，Cr，Mo，W，Ti，Zr，Hf，Fe，Co，Ni，Pt，Pd，Rh，Ir，Ru，Os和镧系元素，至少含有20-60原子％ S，Se和Te的第三要素组的一个元素。 第二层含有5-50原子％的第一元素基团的至少一个元素，10-50原子％的第二元素基团的至少一个元素和30-70原子％的氧。

公开(公告)号：US20110049454A1

公开(公告)日：2011-03-03

申请号：US12305890

申请日：2006-06-23

申请人： Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

发明人： Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

IPC分类号： H01L45/00

CPC分类号： H01L45/1675 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

摘要： In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.

摘要翻译： 在相变存储器中，界面层插入硫族化物材料层和插塞之间。 界面层被布置成不覆盖插塞状电极的整个界面。 当塞子形成在比硫族化物层的上部时，积分度增加。 通过使用氧化物靶进行溅射而形成界面层，或者通过使用金属靶进行溅射而形成金属膜，然后在氧自由基，氧等离子体等的氧化气氛中氧化金属膜。

公开(公告)号：US20060274593A1

公开(公告)日：2006-12-07

申请号：US11501118

申请日：2006-08-09

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

IPC分类号： G11C17/18

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/76 ,  G11C2213/79

摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

公开(公告)号：US07123535B2

公开(公告)日：2006-10-17

申请号：US11002245

申请日：2004-12-03

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

IPC分类号： G11C17/18

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/76 ,  G11C2213/79

摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

公开(公告)号：US07489552B2

公开(公告)日：2009-02-10

申请号：US11501118

申请日：2006-08-09

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

IPC分类号： G11C11/34

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/76 ,  G11C2213/79

摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

摘要翻译： 在非易失性相变存储器中，利用相变部分的电阻变化来记录信息。 当相变部分产生焦耳热并保持在特定温度时，其进入低电阻状态。 当控制存储单元选择晶体管QM的栅极电压以提供低电阻状态时，通过向控制栅极施加中等电压来限制施加到相变部分的最大电流量，从而避免过热 的相变部。

公开(公告)号：US08319204B2

公开(公告)日：2012-11-27

申请号：US12373185

申请日：2006-07-21

申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki

发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki

IPC分类号： H01L45/00 ,  H01L27/04

CPC分类号： G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。

公开(公告)号：US20090039335A1

公开(公告)日：2009-02-12

申请号：US12162769

申请日：2006-02-09

申请人： Motoyasu Terao ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Satoru Hanzawa

发明人： Motoyasu Terao ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Satoru Hanzawa

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  G11C13/0004 ,  G11C13/0011 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： On an insulating film (31) in which a plug (35) is embedded, a second component releasing region (45) made of a first component and a second component, a solid electrolyte region (46) made of chalcogenide and an upper electrode region (47) are sequentially formed. The second component releasing region (45) made of a first component and a second component is composed of dome-shaped electrode portions (43) and an insulating film (44) burying the peripheries of the electrode portions (43), and at least one electrode portion (43) exists on the plug (34). The electrode portion (43) is composed of a first portion made of the first component such as tantalum oxide that is stable even when electric field is applied thereto and a second portion made of the second component such as copper or silver that is easily diffused in the solid electrolyte region (42) and moves therein by the application of an electric field. The second component supplied from the electrode portion (43) moves in the solid electrolyte region (46), thereby storing the information.

摘要翻译： 在其中嵌入有插塞（35）的绝缘膜（31）上，由第一部件和第二部件制成的第二部件释放区域（45），由硫族化物制成的固体电解质区域（46）和上部电极区域 （47）。 由第一部件和第二部件制成的第二部件释放区域（45）由埋入电极部分（43）的周边的圆顶状电极部分（43）和绝缘膜（44）组成，并且至少一个 电极部分（43）存在于插头（34）上。 电极部（43）由第一部分（例如氧化钽）构成的第一部分，即使施加电场也是稳定的，而由诸如铜或银的第二部分制成的第二部分容易扩散 固体电解质区域（42）并通过施加电场而在其中移动。 从电极部（43）供给的第二部件在固体电解质区域（46）中移动，从而存储信息。

公开(公告)号：US20100072451A1

公开(公告)日：2010-03-25

申请号：US12373185

申请日：2006-07-21

申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki

发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki

IPC分类号： H01L45/00 ,  H01L27/04

CPC分类号： G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。

公开(公告)号：US08618523B2

公开(公告)日：2013-12-31

申请号：US12302740

申请日：2006-05-31

申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

IPC分类号： H01L47/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

公开(公告)号：US08000126B2

公开(公告)日：2011-08-16

申请号：US12522744

申请日：2007-01-11

申请人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

发明人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

IPC分类号： G11C11/00 ,  H01L29/66

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.

摘要翻译： 相变存储器由形成在半导体衬底上的绝缘膜中的埋入通孔内的插塞形成，形成在绝缘膜上的界面层，其中埋入插塞，由硫化物层形成的记录层形成在 界面层和形成在记录层上的上接触电极。 根据电阻值变化存储信息的记录层由含有20原子％至38原子％的量的铟的含量为9原子％至28原子％的锗的硫属化物材料制成，3原子级的锑 ％〜18原子％，碲为42原子％〜63原子％，锗的含量大于或等于锑的含量。