-
公开(公告)号：US6023407A
公开(公告)日：2000-02-08
申请号：US31235
申请日：1998-02-26
申请人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
CPC分类号： H01L28/40 , H01G4/306 , Y10T29/435
摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 .mu.m thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 .mu.m for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译： 提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。 还提出了一种用于制造中介层薄膜电容器的方法。 为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10μm的厚的第一金属层沉积在衬底上 然后施加剩余的薄膜，包括电介质膜和第二金属层。 第一金属层包括Pt或其它电极金属，或Pt，Cr和Cu金属的组合以及扩散阻挡层。 另外的Ti层可以用于附着增强。 对于Cr层，第一金属层的厚度约为：200A; Cu层为0.5-10μm; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。
-
公开(公告)号：US06216324B1
公开(公告)日：2001-04-17
申请号：US09382536
申请日：1999-08-25
申请人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
IPC分类号： H01G4002
CPC分类号： H01L28/40 , H01G4/306 , Y10T29/435
摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译： 提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。 还提出了一种用于制造中介层薄膜电容器的方法。 为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10毫米的厚的第一金属层沉积在衬底上，衬底上沉积 然后施加包括电介质膜和第二金属层的剩余薄膜。 第一金属层由Pt或其他电极金属或Pt，Cr和Cu金属的组合以及扩散阻挡层组成。 另外的Ti层可以用于附着增强。 对于Cr层，第一金属层的厚度约为：200A; 铜层为0.5-10毫米; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。
-
3.发明授权公开(公告)号：US06430030B2
公开(公告)日：2002-08-06
申请号：US09770357
申请日：2001-01-26
IPC分类号： H01G406
CPC分类号： H05K1/162 , H01G4/30 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/09701 , H01L2924/15311 , H01L2924/15312 , H01L2924/19103 , H05K1/0306 , H05K1/115 , H05K2201/0187 , H05K2201/09581 , Y10T156/1056 , Y10T156/1057 , Y10T156/107
摘要： A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.
摘要翻译： 一种多层陶瓷电容器和制造该电容器的方法，该电容器具有由包含具有低介电常数的材料的区域包围的信号通孔，插入在具有高介电常数的材料中的低介电常数材料的通孔和周围区域 。
-
4.发明授权Method for making high k dielectric material with low k dielectric sheathed signal vias 失效用于制造具有低k电介质护套信号通孔的高k电介质材料的方法公开(公告)号：US06200400B1
公开(公告)日：2001-03-13
申请号：US09465134
申请日：1999-12-16
IPC分类号： B32B3126
CPC分类号： H05K1/162 , H01G4/30 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/09701 , H01L2924/15311 , H01L2924/15312 , H01L2924/19103 , H05K1/0306 , H05K1/115 , H05K2201/0187 , H05K2201/09581 , Y10T156/1056 , Y10T156/1057 , Y10T156/107
摘要： A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.
摘要翻译： 一种多层陶瓷电容器和制造该电容器的方法，该电容器具有由包含具有低介电常数的材料的区域包围的信号通孔，插入具有高介电常数的材料中的低介电常数材料的通孔和周围区域 。
-
公开(公告)号：US6072690A
公开(公告)日：2000-06-06
申请号：US7624
申请日：1998-01-15
IPC分类号： H01G4/12 , H01G4/30 , H01G4/35 , H01L23/498 , H01L23/50 , H05K1/03 , H05K1/11 , H05K1/16 , H01G4/06 , H01G4/33
CPC分类号： H05K1/162 , H01G4/30 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/09701 , H01L2924/15311 , H01L2924/15312 , H01L2924/19103 , H05K1/0306 , H05K1/115 , H05K2201/0187 , H05K2201/09581 , Y10T156/1056 , Y10T156/1057 , Y10T156/107
摘要： A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.
摘要翻译： 一种多层陶瓷电容器和制造该电容器的方法，该电容器具有由包含具有低介电常数的材料的区域包围的信号通孔，插入具有高介电常数的材料中的低介电常数材料的通孔和周围区域 。
-
公开(公告)号：US06713686B2
公开(公告)日：2004-03-30
申请号：US10053362
申请日：2002-01-18
申请人： Wiren D. Becker , Dinesh Gupta , Sudipta K. Ray , Robert A. Rita , Herbert I. Stoller , Kathleen M. Wiley
发明人： Wiren D. Becker , Dinesh Gupta , Sudipta K. Ray , Robert A. Rita , Herbert I. Stoller , Kathleen M. Wiley
IPC分类号： H01R1204
CPC分类号： H01L23/5382 , H01L2924/0002 , H01L2924/09701 , H05K1/0292 , H05K1/113 , Y10T29/49155 , H01L2924/00
摘要： A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.
摘要翻译： 多芯片模块基板，其布置有在模块的芯片位置的修复通道之间延伸的修理通孔和修复线，通过该维修线可以进行修理以克服模块电路中的缺陷，以及用于实现该电路中的缺陷的修复的方法 模块。 在第一信号通孔，第二信号通孔以及在第一信号通孔和第二信号通孔之间延伸并且用于电连接第一信号通孔的电路线中的任何一个中可能会发生缺陷。 识别出故障电路后，电路的信号通孔被隔离。 然后，故障电路的第一信号通路经由具有第一信号的芯片位置的修复通孔经由与具有第二信号通路的芯片位置的修复通路连接，并且具有缺陷电路的第二信号通孔 电路经由具有第二信号的芯片位置的修复通路经由与经由具有第一信号通孔的芯片位置的修复通路相连接。
-
公开(公告)号：US06878608B2
公开(公告)日：2005-04-12
申请号：US09870531
申请日：2001-05-31
IPC分类号： H01L21/48 , H01L21/68 , H01L21/46 , H01L21/30 , H01L21/302 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/6835 , H01L21/486 , H01L24/16 , H01L2221/6834 , H01L2221/68345 , H01L2221/68354 , H01L2221/68363 , H01L2224/16237 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Forming via holes which extend through the UTSW, forming metallization in the via holes which extends through the UTSW, making electrical contact to the interconnection structure on the first surface. Then bond the metallization in the via holes to pads of a carrier.
摘要翻译： 基于硅的封装（SBP）从用作SBP的基底的厚晶片开始形成，所述基板由具有平坦的第一表面和反面的硅组成。 然后在第一表面上形成包括多层导体图案的互连结构。 在SBP和晶片保持器之间形成临时结合，晶片保持器是刚性结构。 将晶片细化至所需厚度，以形成SBP的超薄硅片（UTSW）。 形成穿过UTSW的孔，在穿过UTSW的通孔中形成金属化，与第一表面上的互连结构电接触。 然后将通孔中的金属化物接合到载体的焊盘。
-
8.发明授权Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules 有权在芯片载体模块中具有非积分间距比的电网之间布线平移的慢跑结构公开(公告)号：US06762489B2
公开(公告)日：2004-07-13
申请号：US09989666
申请日：2001-11-20
申请人： Glenn G. Daves , Jason Frankel , William F. Shutler , Anthony Wayne Sigler , Herbert I. Stoller , John Vetrero , Cathy Ann Zadany
发明人： Glenn G. Daves , Jason Frankel , William F. Shutler , Anthony Wayne Sigler , Herbert I. Stoller , John Vetrero , Cathy Ann Zadany
IPC分类号： H01L2348
CPC分类号： H01L24/17 , H01L23/49833 , H01L23/49838 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2924/01005 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H05K1/0289 , H05K1/112
摘要： A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.
摘要翻译： 公开了一种用于将布线连接从第一网格中的点转换到芯片载体模块中的第二网格中的相应点的慢跑结构。 在示例性实施例中，该结构包括耦合到第一格栅的第一平移层，第一平移层沿x轴方向平移第一格栅。 第二平移层耦合到第一平移层，第二平移层用于在y轴方向上从第一栅格平移所述布线连接，y轴方向与x轴方向正交。 第二平移层还耦合到第二栅极。
-
公开(公告)号：US5243140A
公开(公告)日：1993-09-07
申请号：US771707
申请日：1991-10-04
申请人： Harsaran S. Bhatia , Mario J. Interrante , Suresh D. Kadakia , Shashi D. Malaviya , Mark H. McLeod , Sudipta K. Ray , Herbert I. Stoller
发明人： Harsaran S. Bhatia , Mario J. Interrante , Suresh D. Kadakia , Shashi D. Malaviya , Mark H. McLeod , Sudipta K. Ray , Herbert I. Stoller
IPC分类号： H01L23/12 , H01L21/48 , H01L23/538
CPC分类号： H01L23/5382 , H01L21/485 , H01L2224/16225 , H01L2924/19107
摘要： A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.
-
10.发明授权Method and manufacture of silicon based package and devices manufactured thereby 有权由此制造的硅基封装和器件的制造方法公开(公告)号：US08097492B2
公开(公告)日：2012-01-17
申请号：US12344095
申请日：2008-12-24
IPC分类号： H01L21/50
CPC分类号： H01L21/486 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/147 , H01L24/16 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68345 , H01L2221/68354 , H01L2221/68363 , H01L2224/05571 , H01L2224/16225 , H01L2224/16237 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/0401 , H01L2924/00012
摘要： A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.
摘要翻译： 基于硅的封装（SBP）由从作为SBP的基底的厚晶片开始形成，该基板由具有平坦的第一表面和反面的硅组成。 然后形成包括与第一表面接触的金属捕获结构和在第一表面上的多层导体图案的互连结构。 在SBP和晶片保持器之间形成临时结合，晶片保持器是刚性结构。 将晶圆的反面变薄到所需的厚度，以形成用于SBP的超薄硅晶片（UTSW）。 通过具有锥形或垂直侧壁的孔形成，其延伸穿过UTSW以到达金属捕获结构。 然后在穿过UTSW的通孔中形成金属焊盘，使其与金属捕获结构电接触。 然后将通孔中的金属焊盘接合到载体的焊盘。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.039 秒)