公开(公告)号：US11917813B2

公开(公告)日：2024-02-27

申请号：US17528617

申请日：2021-11-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L27/108 ,  H10B12/00

CPC分类号： H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34

摘要： The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

公开(公告)号：US11894268B2

公开(公告)日：2024-02-06

申请号：US17573793

申请日：2022-01-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/528

CPC分类号： H01L21/76889 ,  H01L21/32133 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/53209

摘要： A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layer

公开(公告)号：US10483201B1

公开(公告)日：2019-11-19

申请号：US16171700

申请日：2018-10-26

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L29/417 ,  H01L23/525 ,  H01L29/06 ,  H01H85/08 ,  H01L21/768 ,  H01L21/02

摘要： A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor layer, a first conductor, a second conductor and a fuse. The first conductor is disposed over the semiconductor layer. The second conductor is disposed over the first conductor. The fuse is disposed between the first conductor and the second conductor, wherein the fuse includes a conductive portion and a non-conductive portion surrounded by the conductive portion, the conductive portion is in contact with the first conductor and the second conductor, and the non-conductive portion is in contact with the second conductor.

公开(公告)号：US20210288007A1

公开(公告)日：2021-09-16

申请号：US17334104

申请日：2021-05-28

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/768

摘要： The present application discloses a method for fabricating a semiconductor device with liners. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, inwardly forming a trench on the first surface of the substrate, forming a plurality of liners positioned on side surfaces of the trench, forming a first insulating segment filling the trench, and removing part of the substrate from the second surface to expose the first insulating segment and the plurality of liners.

公开(公告)号：US11908693B2

公开(公告)日：2024-02-20

申请号：US17669556

申请日：2022-02-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76831 ,  H01L21/76843

摘要： A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.

公开(公告)号：US11610895B2

公开(公告)日：2023-03-21

申请号：US17319562

申请日：2021-05-13

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L27/108

摘要： A method of manufacturing a semiconductor memory device includes providing a substrate with a drain, a source and a gate structure disposed on the substrate between the drain and the source; forming a first inter-layer dielectric covering the substrate and the gate structure; forming a plug in the first inter-layer dielectric, with a first part contacting the source of the substrate. In the next step, a second part of the plug is exposed through the first inter-layer dielectric, and a storage node landing pad is formed on the exposed second part of the plug; a second inter-layer dielectric is formed on the first inter-layer dielectric, covering the storage node landing pad; a bit line is formed, connected to the substrate through the second inter-layer dielectric and the first inter-layer dielectric; a third inter-layer dielectric is formed on the bit line; and, a storage node is formed on the third inter-layer dielectric.

公开(公告)号：US11462519B2

公开(公告)日：2022-10-04

申请号：US16889218

申请日：2020-06-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L23/495 ,  H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.

公开(公告)号：US11107785B2

公开(公告)日：2021-08-31

申请号：US16582191

申请日：2019-09-25

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L23/00 ,  H01L27/108

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of conductive features positioned above the substrate, a plurality of landing pads positioned above the substrate, a coverage layer positioned above the substrate, and a plurality of capacitor structures positioned above the substrate. An angle between the axes of two adjacent landing pads is less than 180 degrees.

公开(公告)号：US11101229B2

公开(公告)日：2021-08-24

申请号：US16573549

申请日：2019-09-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/768

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first conductive body, a second conductive body positioned separate from the first conductive body, a plurality of liners respectively correspondingly attached to a side surface of the first conductive body and a side surface of the second conductive body, and a first insulating segment positioned between the first conductive body and the second conductive body.

公开(公告)号：US11063049B2

公开(公告)日：2021-07-13

申请号：US16421024

申请日：2019-05-23

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L27/108

摘要： A semiconductor memory device includes a substrate with a drain and a source; a gate structure, disposed on the substrate between the drain and the source; a first dielectric, disposed on the substrate, covering the gate structure; a second dielectric disposed on the first dielectric; a plug having a first part in the first dielectric and a second part in the second dielectric, wherein the first part is in contact with the source of the substrate; a storage node landing pad, covering the second part of the plug and covered by the second dielectric; a bit line disposed on the second dielectric and connected to the drain of the substrate; a third dielectric disposed on the bit line; and a storage node, disposed on the third dielectric, contacting the storage node landing pad through the second dielectric and the third dielectric.