-
公开(公告)号：US12160205B2
公开(公告)日：2024-12-03
申请号：US18005928
申请日：2020-07-21
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Teruo Jo , Munehiko Nagatani , Hideyuki Nosaka
Abstract: An amplifier circuit comprises a variable degeneration circuit connected to emitter terminals of transistors, and a variable negative capacitance circuit connected to differential output signal terminals. The variable degeneration circuit includes a variable capacitor and a resistor. The variable negative capacitance circuit, which is a variable current source, includes a transistor, a capacitor, and a variable current source. The variable negative capacitance circuit includes transistors, a capacitor, and variable current sources.
-
公开(公告)号：US12119962B2
公开(公告)日：2024-10-15
申请号：US17630375
申请日：2019-08-05
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
CPC classification number: H04L25/0272 , G01R27/32 , G01R31/2813 , G01R31/58 , G06F3/05 , H03M1/126
Abstract: A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.
-
公开(公告)号：US20240120883A1
公开(公告)日：2024-04-11
申请号：US18546172
申请日：2021-02-18
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Teruo Jo , Munehiko Nagatani , Hideyuki Nosaka
IPC: H03B5/24
CPC classification number: H03B5/24
Abstract: A voltage-controlled oscillator includes a first unit cell, a second unit cell that is connected in parallel to the first unit cell via transmission lines, a compensation unit cell that is connected in parallel with the first unit cell and the second unit cell between the first unit cell and the second unit cell, and an input termination resistor that is connected to a power supply voltage terminal of each of the first unit cell, the second unit cell, and the compensation unit cell. Symmetrical voltages are supplied to the first unit cell and the second unit cell, and the compensation unit cell compensates for a gain by the first unit cell or the second unit cell.
-
公开(公告)号：US20230336185A1
公开(公告)日：2023-10-19
申请号：US17768168
申请日：2019-10-23
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Munehiko Nagatani , Teruo Jo , Hiroshi Yamazaki , Hideyuki Nosaka
IPC: H03M1/12 , H03K17/693
CPC classification number: H03M1/1255 , H03M1/1295 , H03K17/693
Abstract: An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).
-
公开(公告)号：US20230299724A1
公开(公告)日：2023-09-21
申请号：US18005928
申请日：2020-07-21
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Teruo Jo , Munehiko Nagatani , Hideyuki Nosaka
CPC classification number: H03F1/42 , H03F3/45179 , H03F2200/36
Abstract: An amplifier circuit comprises a variable degeneration circuit connected to emitter terminals of transistors, and a variable negative capacitance circuit connected to differential output signal terminals. The variable degeneration circuit includes a variable capacitor and a resistor. The variable negative capacitance circuit, which is a variable current source, includes a transistor, a capacitor, and a variable current source. The variable negative capacitance circuit includes transistors, a capacitor, and variable current sources.
-
公开(公告)号：US20230288735A1
公开(公告)日：2023-09-14
申请号：US18006124
申请日：2020-07-21
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Teruo Jo , Munehiko Nagatani , Hideyuki Nosaka
CPC classification number: G02F1/0121 , H02H9/044
Abstract: An embodiment includes an output circuit with transistors and a withstand voltage protection circuit. The withstand voltage protection circuit includes resistors connected between an output signal terminal on the positive phase side and an output signal terminal on the negative phase side. A switch includes an NMOS transistor having a gate terminal connected to the connection point of the resistors, a drain terminal connected to the bias voltage, and a source terminal connected to the base terminal of the transistor.
-
公开(公告)号：US20230246616A1
公开(公告)日：2023-08-03
申请号：US18002919
申请日：2020-06-26
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Teruo Jo , Munehiko Nagatani , Hideyuki Nosaka
Abstract: An embodiment is a multiplexer including a first distributed amplifier with an impedance matched to 50Ω, the first distributed amplifier configured to receive a first signal and output a first amplified signal, a second distributed amplifier with an impedance matched to 50Ω, the second distributed amplifier configured to receive a second signal and output a second amplified signal, and a passive multiplexer configured to multiplex the first amplified signal and the second amplified signal, and output a multiplexed signal to a signal output terminal, the passive multiplexer including a first resistor having a first end to receive the first amplified signal, a second resistor having a first end to receive the second amplified signal, and a third resistor having a first end connected to second ends of the first and second resistors and a second end connected to the signal output terminal.
-
公开(公告)号：US20210194523A1
公开(公告)日：2021-06-24
申请号：US17053237
申请日：2019-04-22
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Teruo Jo , Munehiko Nagatani , Hiroshi Hamada , Hiroyuki Fukuyama , Hideyuki Nosaka , Hiroshi Yamazaki
Abstract: A digital signal process unit includes a first cancel signal generation unit and a second cancel signal generation unit. The first cancel signal generation unit generates, as a first cancel signal component, a cancel signal component corresponding to an image signal included in an analog signal output from a mixer. The second cancel signal generation unit generates, as a second cancel signal component, a cancel signal component corresponding to a leakage signal generated between an input and output of the mixer. The digital signal process unit includes subtractors for subtracting the first cancel signal component and the second cancel signal component from a signal component corresponding to a frequency band divided from an input signal to obtain a digital signal.
-
公开(公告)号：US20210091533A1
公开(公告)日：2021-03-25
申请号：US16971046
申请日：2019-02-22
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Toshiki Kishi , Munehiko Nagatani , Shinsuke Nakano , Hideyuki Nosaka
Abstract: A CMOS inverter circuit is provided as a circuit to modulate a current flowing into a laser diode on the basis of a digital signal. An amplitude of a current flowing in a PMOSFET in the CMOS inverter circuit is made to contribute to an amplitude of the current flowing into the laser diode, to reduce an input amplitude.
-
公开(公告)号：US10177780B2
公开(公告)日：2019-01-08
申请号：US15754033
申请日：2016-08-19
Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Inventor： Hiroshi Yamazaki , Munehiko Nagatani , Hideyuki Nosaka , Akihide Sano , Yutaka Miyamoto
Abstract: In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer.
