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公开(公告)号:US20220247423A1
公开(公告)日:2022-08-04
申请号:US17616643
申请日:2020-01-07
申请人: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人: DAIGUO XU , HEQUAN JIANG , RUZHANG LI , JIANAN WANG , GUANGBING CHEN , YUXIN WANG , DONGBING FU , LIANG LI , YAN WANG
摘要: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.
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公开(公告)号:US20220091184A1
公开(公告)日:2022-03-24
申请号:US17602993
申请日:2020-01-07
申请人: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人: MINGYUAN XU , LIANG LI , JUN LIU , XIAOFENG SHEN , JIANAN WANG , DONGBING FU , GUANGBING CHEN , XINGFA HUANG , XI CHEN
IPC分类号: G01R31/317 , H03K19/0948
摘要: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK−) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK−) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.
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