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公开(公告)号：US09621138B1
公开(公告)日：2017-04-11
申请号：US14933442
申请日：2015-11-05
Applicant: NXP B.V.
Inventor： Xu Zhang , Siamak Delshadpour , Ahmad Yazdi
IPC: H03K5/12 , H03K5/01 , H03K19/0185 , H03K3/353
CPC classification number: H03K5/01 , H03K3/353 , H03K17/16 , H03K19/00361 , H03K19/018507 , H03K19/018585
Abstract: An apparatus includes a swing control circuit, a slew control circuit, and a driver circuit. The swing control circuit is configured and arranged to be powered by an input supply voltage, to receive an input data signal and, in response, to generate a first internal signal having a swing level corresponding to the input supply voltage. The slew control circuit, including a switched capacitor circuit, is configured and arranged to receive the first internal signal and, in response, to generate a second internal signal using the switched capacitor circuit that is configured to set a slew rate for the second internal signal. Further, the driver circuit is configured and arranged to receive the second internal signal and, in response, to generate an output signal that is based upon the swing level and the slew rate of the second internal signal.
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公开(公告)号：US10976351B2
公开(公告)日：2021-04-13
申请号：US16273230
申请日：2019-02-12
Applicant: NXP B.V.
Inventor： Xu Zhang , Siamak Delshadpour , Ahmad Yazdi
IPC: G01R15/14 , G01R19/165 , G01R19/25 , G01R27/08 , G01R27/16
Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.
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3.发明授权公开(公告)号：US10917055B2
公开(公告)日：2021-02-09
申请号：US16184921
申请日：2018-11-08
Applicant: NXP B.V.
Inventor： Xueyang Geng , Siamak Delshadpour , Soon-Gil Jung , Ahmad Yazdi
Abstract: A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.
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公开(公告)号：US10862720B2
公开(公告)日：2020-12-08
申请号：US16154196
申请日：2018-10-08
Applicant: NXP B.V.
Inventor： Siamak Delshadpour , Xueyang Geng , Ahmad Yazdi
Abstract: Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.
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公开(公告)号：US10910998B2
公开(公告)日：2021-02-02
申请号：US16135224
申请日：2018-09-19
Applicant: NXP B.V.
Inventor： Siamak Delshadpour , Ahmad Yazdi , Xueyang Geng
IPC: H03C3/09 , H04B1/10 , H03L7/099 , H03L7/089 , H03G3/34 , H03K5/24 , H03H11/12 , H04B17/11 , H04B1/16 , H04B17/21 , H04B1/04 , H04B1/405
Abstract: Various embodiments relate to a method for calibration of a center frequency of a BPF in an FSK transceiver, the method including the steps of filtering a carrier frequency signal by the BPF to produce a filtered signal, detecting, by a phase-frequency detector (“PFD”), a difference in phase between the carrier frequency signal and the filtered signal from the BPF, sweeping a calibration code of the BPF, detecting a transition in the sign of the phase difference and capturing a calibration code associated with the transition in the sign of the phase difference for calibration of the BPF.
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Patent Agency Ranking
公开(公告)号：US20200256894A1
公开(公告)日：2020-08-13
申请号：US16273230
申请日：2019-02-12
Applicant: NXP B.V.
Inventor： Xu Zhang , Siamak Delshadpour , Ahmad Yazdi
IPC: G01R15/14 , G01R19/25 , G01R19/165 , G01R27/16 , G01R27/08
Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.
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公开(公告)号：US10560080B1
公开(公告)日：2020-02-11
申请号：US16183698
申请日：2018-11-07
Applicant: NXP B.V.
Inventor： Xu Zhang , Siamak Delshadpour , Ahmad Yazdi
IPC: H03K5/156
Abstract: A duty cycle correction circuit is disclosed. The duty cycle correction circuit includes an input stage, an output stage and a feedback component including a feedback amplifier and a low pass filter. The feedback component compares and adjusts the duty cycle of a signal from an input stage to a target value via a control voltage. The input stage reduces the rise and fall times of received signal to increase the duty cycle sensitivity to a control voltage from the feedback component. The output of the output stage is coupled to the input of the feedback component and the output stage amplifiers the duty cycle adjusted signal processed by both input stage and feedback component.
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公开(公告)号：US10003192B2
公开(公告)日：2018-06-19
申请号：US14868044
申请日：2015-09-28
Applicant: NXP B.V.
Inventor： Xueyang Geng , Ahmad Yazdi , Siamak Delshadpour , Abhijeet Chandrakant Kulkarni
Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.
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公开(公告)号：US20170093154A1
公开(公告)日：2017-03-30
申请号：US14868044
申请日：2015-09-28
Applicant: NXP B.V.
Inventor： Xueyang Geng , Ahmad Yazdi , Siamak Delshadpour , Abhijeet Chandrakant Kulkarni
Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.
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10.发明申请公开(公告)号：US20200153395A1
公开(公告)日：2020-05-14
申请号：US16184921
申请日：2018-11-08
Applicant: NXP B.V.
Inventor： Xueyang Geng , Siamak Delshadpour , Soon-Gil Jung , Ahmad Yazdi
Abstract: A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.
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