公开(公告)号：US09349819B2

公开(公告)日：2016-05-24

申请号：US14714927

申请日：2015-05-18

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Stephen John Sque ,  Andreas Bernardus Maria Jansman ,  Markus Mueller ,  Stephan Heil ,  Tim Boettcher

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/47 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L21/02362 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/417 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/872

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract translation: 公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分 用于局部增加肖特基电极的肖特基势垒。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20140167064A1

公开(公告)日：2014-06-19

申请号：US14108042

申请日：2013-12-16

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Stephan Heil ,  Jan Sonsky

IPC: H01L29/47 ,  H01L29/872 ,  H01L29/778 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A GaN hetereojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectric layer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.

Abstract translation: GaN半导体结构具有三层电介质结构。 栅电极的最下部和中部一起限定栅极脚，并且这与两个电介质层相关联。 较薄的第一介电层与栅极底部的栅极边缘相邻。 第二电介质层对应于传统结构中的层，并且与栅极脚的主要部分平齐。

公开(公告)号：US08962461B2

公开(公告)日：2015-02-24

申请号：US14108042

申请日：2013-12-16

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Stephan Heil ,  Jan Sonsky

IPC: H01L21/28 ,  H01L21/44 ,  H01L29/47 ,  H01L29/40 ,  H01L29/778 ,  H01L29/872 ,  H01L23/31 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/475 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.

Abstract translation: 与示例性实施例一致，GaN异质结结构具有三层电介质结构。 栅电极的最下部和中部一起限定栅极脚，并且这与两个电介质层相关联。 较薄的第一介电层与栅极底部的栅极边缘相邻。 第二电介质层对应于常规结构中的层，并且与栅极脚的主要部分平齐。

公开(公告)号：US09793348B2

公开(公告)日：2017-10-17

申请号：US14946064

申请日：2015-11-19

Applicant: NXP B.V.

Inventor： Jan Sonsky

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L29/267

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1207 ,  H01L29/267

Abstract: A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.

公开(公告)号：US20170170089A1

公开(公告)日：2017-06-15

申请号：US15356519

申请日：2016-11-18

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Mark Andrzej Gajda ,  Jan Sonsky

IPC: H01L23/31 ,  H01L29/205 ,  H01L21/56 ,  H01L29/872 ,  H01L23/29 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L23/3171 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon

公开(公告)号：US20170062419A1

公开(公告)日：2017-03-02

申请号：US15233785

申请日：2016-08-10

Applicant: NXP B.V.

Inventor： Matthias Rose ,  Jan Sonsky

IPC: H01L27/088 ,  H01L29/16 ,  H02M3/158 ,  H01L29/872 ,  H01L21/8236 ,  H01L29/20 ,  H01L27/02

CPC classification number: H01L27/0883 ,  H01L21/8236 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/513 ,  H01L29/778 ,  H01L29/872 ,  H02M3/158 ,  H03K17/6871

Abstract: A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an insulated-gate-depletion-mode-transistor provided on the semiconductor-die, the insulated-gate-depletion-mode-transistor comprising a depletion-source-terminal, a depletion-drain-terminal and a depletion-gate-terminal, wherein the depletion-drain-terminal is coupled to the die-drain-terminal and the depletion-gate-terminal is coupled to the die-source-terminal; an enhancement-mode-transistor comprising an enhancement-source-terminal, an enhancement-drain-terminal and an enhancement-gate-terminal, wherein the enhancement-source-terminal is coupled to the die-source-terminal, the enhancement-gate-terminal is coupled to the die-gate-terminal and the enhancement-drain-terminal is coupled to the depletion-source-terminal; and a clamp-circuit coupled between the depletion-source-terminal and the depletion-gate-terminal.

Abstract translation: 一种半导体器件，包括：芯片 - 源极端子，芯片 - 漏极端子和晶体管 - 栅极端子; 半导体芯片; 设置在所述半导体管芯上的绝缘栅极耗尽型晶体管，所述绝缘栅极耗尽型晶体管包括耗尽源极端子，耗尽 - 漏极端子和耗尽栅极端子，其中 耗尽漏极端子耦合到管芯漏极端子，耗尽栅极端子耦合到管芯源极端子; 增强型晶体管，其包括增强源极端子，增强型 - 漏极端子和增强型栅极端子，其中所述增强源极端子耦合到所述管芯源极端子，所述增强型 - 端子耦合到晶体管栅极端子，并且增强漏极端子耦合到耗尽源极端子; 以及耦合在耗尽源极端与耗尽栅极端子之间的钳位电路。

公开(公告)号：US09472549B2

公开(公告)日：2016-10-18

申请号：US14056648

申请日：2013-10-17

Applicant: NXP B.V.

Inventor： Matthias Rose ,  Jan Sonsky ,  Philip Rutter

IPC: H01H47/00 ,  H01L27/088 ,  H01L27/08 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74

CPC classification number: H01L27/088 ,  H01L27/0814 ,  H03K17/567 ,  H03K17/6871 ,  H03K17/6874 ,  H03K17/74 ,  H03K2017/6875

Abstract: A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.

Abstract translation: 级联功率半导体电路在氮化镓或碳化硅FET的源极和栅极之间具有钳位电路，以提供共源共栅MOSFET晶体管的雪崩保护。

公开(公告)号：US09391187B2

公开(公告)日：2016-07-12

申请号：US14723247

申请日：2015-05-27

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Stephan Bastiaan Simon Heil ,  Jan Sonsky

IPC: H01L29/20 ,  H01L29/36 ,  H01L29/778 ,  H01L29/205 ,  H01L29/32 ,  H01L29/417 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/66143 ,  H01L29/7786 ,  H01L29/872

Abstract: In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

Abstract translation: 在示例性实施例中，异质结装置包括衬底，设置在衬底上的多层结构。 所述多层结构具有设置在所述基板顶部的具有第一半导体的第一层; 第二层具有第二半导体设置在第一层的顶部，限定它们之间的界面。 第二半导体与第一半导体不同，使得2D电子气体与界面相邻形成。 第一端子耦合到第一和第二层之间的界面的第一区域，并且第二端子耦合到第一层和第二层之间的界面的第二区域; 导电通道包括具有比第一层的另一区域更高的缺陷密度的第一层的金属或区域。 通道连接第二端子和第一层的区域，使得电荷在它们之间流动。

公开(公告)号：US08853816B2

公开(公告)日：2014-10-07

申请号：US13705627

申请日：2012-12-05

Applicant: NXP B.V.

Inventor： Peter Gerard Steeneken ,  Roel Daamen ,  Gerard Koops ,  Jan Sonsky ,  Evelyne Gridelet ,  Coenraad Cornelis Tak

IPC: H01L21/70 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/823878

Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.

Abstract translation: 一种隔离半导体电路，包括：第一子电路和第二子电路; 后端，其包括在所述第一和第二子电路之间的电隔离连接器; 在所述第一和第二子电路的半导体部分之间的横向隔离沟槽，其中所述横向隔离沟槽沿着所述第一和第二子电路的半导体部分的宽度延伸，其中所述隔离沟槽的一端与所述后端 ，并且其中所述隔离沟槽填充有电绝缘材料。

公开(公告)号：US20150229205A1

公开(公告)日：2015-08-13

申请号：US14613235

申请日：2015-02-03

Applicant: NXP B.V.

Inventor： Henricus Cornelis Johannes Buthker ,  Matthias Rose ,  Philip Rutter ,  Jan Sonsky

IPC: H02M1/42 ,  H02M7/06

CPC classification number: H02M1/4225 ,  H02M3/155 ,  H02M7/06 ,  H02M2001/0048 ,  Y02B70/126 ,  Y02B70/1491 ,  Y02P80/112

Abstract: Embodiments relate to a diode circuit which uses a Schottky diode. A parallel bypass branch has a switch and bypass diode in series. The operation of the switch is dependent on the voltage across the Schottky diode so that the bypass function is only effective when a desired voltage is reached. The diode circuit can be used as a replacement for a single diode, and provides bypass current protection preferably without requiring any external control input.

Abstract translation: 实施例涉及使用肖特基二极管的二极管电路。 并联旁路支路具有串联的开关和旁路二极管。 开关的操作取决于肖特基二极管两端的电压，因此旁路功能仅在达到所需电压时有效。 二极管电路可以用作单个二极管的替代，并且提供旁路电流保护，优选地不需要任何外部控制输入。