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1.发明授权System direct memory access (DMA) support logic for PCI based computer system 失效用于基于PCI的计算机系统的系统直接存储器访问（DMA）支持逻辑
公开(公告)号：US5450551A
公开(公告)日：1995-09-12
申请号：US68477
申请日：1993-05-28
IPC分类号： G06F13/28 , G06F13/30 , G06F13/36 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4018 , G06F13/30 , G06F13/36
摘要： A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
摘要翻译： 提供直接存储器访问（DMA）支持机制用于计算机系统，其包括（i）通过第一系统总线连接到系统存储器的中央处理单元（CPU）和连接到CPU的第二系统总线; （ii）将第二系统总线连接到外围总线的主桥; （iii）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，标准I / O总线具有连接到其上的多个标准I / O设备; 以及（v）以仲裁模式起作用的仲裁逻辑，用于在竞争访问标准I / O总线的多个标准I / O设备之间进行仲裁，并且在授权模式中，授权选择的标准I / O设备被授权访问 到标准I / O总线。 DMA支持机制包括代表所选标准I / O设备执行DMA周期的直接存储器访问（DMA）控制器，以及直接存储器访问（DMA）支持逻辑，用于通过外设总线执行DMA周期。 DMA支持逻辑包括直接连接DMA控制器与I / O桥的边带信号，边带信号包括识别DMA控制器正在执行DMA周期的所选I / O设备的总线大小的信息。
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公开(公告)号：US5396602A
公开(公告)日：1995-03-07
申请号：US69253
申请日：1993-05-28
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
CPC分类号： G06F13/364 , G06F13/4031
摘要： An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.
摘要翻译： 提供了一种在计算机系统中使用的仲裁机制，其包括（i）中央处理单元（CPU）; （ii）第一系统总线，其将CPU连接到系统存储器，使得CPU可以从系统存储器读取数据并将数据写入系统存储器; （iii）连接到CPU的第二系统总线; （iv）将所述第二系统总线连接到外围总线的主桥，所述外围总线具有附接到其上的至少一个外围设备; 以及（v）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，所述标准I / O总线具有附接到其上的多个标准I / O设备。 仲裁机制包括（i）用于在多个标准I / O设备之间进行仲裁的第一级逻辑，其中从多个标准I / O设备中选择一个标准I / O设备来竞争访问标准I / O总线，以及（ii）用于在所选择的标准I / O设备，CPU和至少一个外围设备之间进行仲裁的第二级逻辑，其中所选择的标准I / O设备，CPU和at 选择至少一个外围设备来访问外围总线。 仲裁机制包括连接第一级仲裁逻辑和第二级仲裁逻辑的边带信号，并包括对应于所选标准I / O设备的仲裁识别信息。
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公开(公告)号：US5333274A
公开(公告)日：1994-07-26
申请号：US778040
申请日：1991-10-15
CPC分类号： G06F13/28 , G06F11/00 , G06F11/0751 , G06F11/0757 , G06F11/0763 , G06F11/1402
摘要： A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.
摘要翻译： 公开了一种具有检测DMA错误状况的错误电路的DMA控制器。 错误电路使得DMA控制器在终止DMA传输之前执行完成任务，有利地提供了一个DMA控制器，它可以在检测到具有错误恢复潜力的错误状况时正常地退出。
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公开(公告)号：US5548786A
公开(公告)日：1996-08-20
申请号：US224123
申请日：1994-04-06
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
CPC分类号： G06F13/28
摘要： A DMA controller is provided for transferring data between source and destination devices over an I/O bus. The DMA control circuit includes a bus interface unit for providing a bus size information at the beginning of each consecutive bus cycle and a look ahead responsive to the bus size information for providing a bus size control signal. A DMA control circuit responsive to the bus size control signal controls the bus width during contiguous transfer cycles. By dynamically adjusting the DMA control circuit, back to back data reads and writes may occur with no wait states inserted for generating the terminal count information.
摘要翻译： 提供DMA控制器用于通过I / O总线在源设备和目标设备之间传输数据。 DMA控制电路包括总线接口单元，用于在每个连续的总线周期的开始处提供总线尺寸信息，并且响应于总线尺寸信息提供前视，用于提供总线尺寸控制信号。 响应于总线尺寸控制信号的DMA控制电路在连续传送周期期间控制总线宽度。 通过动态调整DMA控制电路，背靠背数据读取和写入可能会在没有插入等待状态以产生终端计数信息的情况下进行。
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公开(公告)号：US5619729A
公开(公告)日：1997-04-08
申请号：US584805
申请日：1996-01-11
申请人： Patrick M. Bland , Richard G. Hofmann , Robert T. Jackson , Nader Amini , Bechara F. Boury , Jayesh Joshi
发明人： Patrick M. Bland , Richard G. Hofmann , Robert T. Jackson , Nader Amini , Bechara F. Boury , Jayesh Joshi
CPC分类号： G06F1/3225 , G06F1/3275 , G06F13/28 , Y02B60/1225 , Y02B60/1228
摘要： A device and method for power management of direct memory access ("DMA") slaves through DMA traps. The device comprises a plurality of registers coupled with conventional logic in order to generate a control signal for disabling direct memory access transfer requests for a powered-off DMA slave until the slave is re-powered. The method for managing power comprises steps of unmasking bits in a register containing information regarding which DMA slaves have been powered-off. Next, the DMA Controller consults a power management macro ("PMM") to determine whether a DMA transfer request involves a powered-off DMA slave. If not, the DMA transfer continues. However, if the DMA transfer does involve a powered-off DMA slave, then a main software application in operation is temporarily halted and the PMM generates a SMI signal and outputs the SMI signal to the central processing unit ("CPU") while keeping the disable control signal asserted, which effectively disables the DMA channel. The SMI signal invokes a software service routine which re-powers the powered-off DMA slave so that the main software application can continue.
摘要翻译： 通过DMA陷阱对直接存储器访问（“DMA”）从站进行电源管理的设备和方法。 该装置包括与常规逻辑耦合的多个寄存器，以便产生一个控制信号，用于禁用关闭DMA从器件的直接存储器访问传输请求，直到从器件被重新供电为止。 用于管理功率的方法包括以下步骤：在包含关于哪个DMA从设备已断电的信息的寄存器中取消屏蔽位。 接下来，DMA控制器查询电源管理宏（“PMM”）以确定DMA传输请求是否涉及关闭的DMA从机。 否则，DMA传输继续。 然而，如果DMA传输确实涉及关闭的DMA从器件，则暂时停止正在运行的主要软件应用程序，并且PMM生成SMI信号并将SMI信号输出到中央处理器（“CPU”），同时保持 禁用控制信号有效，从而有效地禁用DMA通道。 SMI信号调用一个软件服务程序，重新供电关闭的DMA从站，使主软件应用程序能够继续运行。
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6.发明授权System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus 失效系统具有总线接口单元，用于在系统资源设备已经获得总线控制之后超越正常的仲裁方案
公开(公告)号：US5544346A
公开(公告)日：1996-08-06
申请号：US353165
申请日：1994-12-09
CPC分类号： G06F13/1605
摘要： An information handling systems capable of transferring data among various system resource devices such as input/output (I/O) devices and a system memory includes a first bus coupled to the system memory, a second bus coupled to the system resource devices, and a bus interface unit (BIU) coupled between the first bus and the second bus. Each of the system resource devices is capable of controlling the second bus after arbitrating therefor. The BIU includes a buffer for temporary storage of data being transferred between the first bus and the second bus, and control logic for generating a lock control signal, after one of the system resource devices has gained control of the second bus by arbitration, to gain control of the first bus to prevent other system resource devices from accessing the first bus. The control signal is dynamically generated by the BIU based on programmable conditions relating to the data transfer, thus optimizing data transfers between the first bus and the second bus. The control signal may act as an override to the normal memory controller arbitration scheme to prioritize access of the system resource devices to the system memory.
摘要翻译： 能够在诸如输入/输出（I / O）设备和系统存储器的各种系统资源设备之间传送数据的信息处理系统包括耦合到系统存储器的第一总线，耦合到系统资源设备的第二总线，以及 总线接口单元（BIU），耦合在第一总线和第二总线之间。 每个系统资源设备在对其进行仲裁之后能够控制第二总线。 BIU包括用于临时存储在第一总线和第二总线之间传输的数据的缓冲器，以及用于在系统资源设备之一通过仲裁获得第二总线的控制之后产生锁定控制信号的控制逻辑，以获得 控制第一总线以防止其他系统资源设备访问第一总线。 基于与数据传输相关的可编程条件，BIU动态地产生控制信号，从而优化第一总线与第二总线之间的数据传输。 控制信号可以作为对正常存储器控制器仲裁方案的覆盖，以优先考虑系统资源设备对系统存储器的访问。
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7.发明授权
公开(公告)号：US5265211A
公开(公告)日：1993-11-23
申请号：US816116
申请日：1992-01-02
IPC分类号： G06F13/28 , G06F13/22 , G06F13/36 , G06F13/362
CPC分类号： G06F13/225 , G06F13/362
摘要： A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.
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8.发明授权DMA controller including a FIFO register and a residual register for data buffering and having different operating modes 失效DMA控制器包括FIFO寄存器和用于数据缓冲的残留寄存器，并具有不同的工作模式
公开(公告)号：US5381538A
公开(公告)日：1995-01-10
申请号：US778042
申请日：1991-10-15
申请人： Nader Amini , Bechara F. Boury , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Terence J. Lohman
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) controller for exchanging data information between a system memory and an input/output (I/O) device in an initial data exchange mode and an alternate data exchange mode includes a register for exchanging the data information during both modes and a residual data register for storing residual data information in the register upon commencement of the alternate data exchange mode and for providing the residual data information when the initial data exchange mode is restarted.
摘要翻译： 用于在初始数据交换模式和备用数据交换模式下在系统存储器和输入/输出（I / O）设备之间交换数据信息的直接存储器访问（DMA）控制器包括用于在两种模式下交换数据信息的寄存器 以及剩余数据寄存器，用于在备用数据交换模式开始时将剩余数据信息存储在寄存器中，并且用于当初始数据交换模式重新启动时提供残留数据信息。
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公开(公告)号：US5301282A
公开(公告)日：1994-04-05
申请号：US777777
申请日：1991-10-15
申请人： Nader Amini , Bechara F. Boury , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Terence J. Lohman
IPC分类号： G06F13/36 , G06F13/30 , G06F13/362
CPC分类号： G06F13/30 , G06F13/362
摘要： An arbiter with an arbitration hold feature is provided which makes it possible to begin an arbitration cycle while information is still being transferred via a bus because the arbiter does not reallocate the bus until the present transfer is complete, as indicated by the arbitration hold feature. Accordingly, arbitration can essentially be overlapped with transfer of information over the bus, thus increasing the amount of information which can be transferred in a given interval of time.
摘要翻译： 提供了具有仲裁保持特征的仲裁器，这使得可以在信息仍然通过总线传送的同时开始仲裁循环，因为仲裁保持特征所示，仲裁器在本转移完成之前不重新分配总线。 因此，仲裁基本上可以与总线上的信息传递重叠，从而增加可以在给定的时间间隔内传送的信息量。
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10.发明授权Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus 失效用于多总线信息处理系统的总线到总线桥，可优化系统总线和外设总线之间的数据传输
公开(公告)号：US5499346A
公开(公告)日：1996-03-12
申请号：US69230
申请日：1993-05-28
CPC分类号： G06F11/10 , G06F11/0793 , G06F11/3027 , G06F11/3055
摘要： An information processing system, comprising a central processing unit (CPU); a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; a second system bus connected to the CPU; a host bridge connecting the second system bus to a peripheral bus having at least one peripheral device attached thereto, the host bridge including register space for storing information related to transactions occurring over the peripheral bus; and error capture logic incorporated into the host bridge. The error capture logic monitors the transactions occurring over the peripheral bus, detects parity errors occurring during any of the transactions, and generates an interrupt routine over the second system bus to the CPU. The CPU reads the register space and performs necessary recovery operations.
摘要翻译： 一种信息处理系统，包括中央处理单元（CPU）; 第一系统总线，其将CPU连接到系统存储器，使得CPU可以从系统存储器读取数据和向其写入数据; 连接到CPU的第二系统总线; 将所述第二系统总线连接到具有连接至少一个外围设备的外围总线的主桥，所述主桥包括用于存储与所述外围总线上发生的事务有关的信息的寄存器空间; 并将错误捕获逻辑并入主桥。 错误捕获逻辑监视通过外设总线发生的事务，检测在任何事务期间发生的奇偶校验错误，并通过第二个系统总线生成中断程序到CPU。 CPU读取寄存器空间并执行必要的恢复操作。
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