公开(公告)号：US08076250B1

公开(公告)日：2011-12-13

申请号：US12899401

申请日：2010-10-06

申请人： Nagarajan Rajagopalan ,  Xinhai Han ,  Ji Ae Park ,  Tsutomu Kiyohara ,  Sohyun Park ,  Bok Hoen Kim

发明人： Nagarajan Rajagopalan ,  Xinhai Han ,  Ji Ae Park ,  Tsutomu Kiyohara ,  Sohyun Park ,  Bok Hoen Kim

IPC分类号： H01L21/31

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0234

摘要： A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.

摘要翻译： 在保持真空的同时，在单个等离子体增强化学气相沉积处理室中的衬底上沉积不同材料的层堆叠。 将衬底放置在处理室中，并且使用第一处理气体在衬底上形成第一材料的第一层。 在使用第二处理气体在基板上形成第二材料的第二层之前进行等离子体吹扫和气体吹扫。 等离子体吹扫和气体吹扫被重复，并且第一和第二材料的附加层沉积在层叠上。

公开(公告)号：US20110136327A1

公开(公告)日：2011-06-09

申请号：US12824032

申请日：2010-06-25

申请人： Xinhai Han ,  Nagarajan Rajagopalan ,  Ji Ae Park ,  Bencherki Mebarki ,  Heung Lak Park ,  Bok Hoen Kim

发明人： Xinhai Han ,  Nagarajan Rajagopalan ,  Ji Ae Park ,  Bencherki Mebarki ,  Heung Lak Park ,  Bok Hoen Kim

IPC分类号： H01L21/329 ,  H01L21/203

CPC分类号： H01L21/0262 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L29/66136 ,  H01L29/868

摘要： Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.

摘要翻译： 描述了在衬底上形成高电流密度垂直p-i-n二极管的方法。 这些方法包括以下步骤：以含有IV族元素的前体和依次暴露于n型掺杂剂前体和p型掺杂剂前体的任一顺序同时组合。 通过在流过含IV族元素的前体的同时减少或消除掺杂剂前体的流动，在n型和p型层之间沉积本征层。 在沉积n型层，本征层和p型层期间，衬底可以驻留在相同的处理室中，并且衬底在相邻层的沉积之间不暴露于大气中。

公开(公告)号：US08298887B2

公开(公告)日：2012-10-30

申请号：US12824032

申请日：2010-06-25

申请人： Xinhai Han ,  Nagarajan Rajagopalan ,  Ji Ae Park ,  Bencherki Mebarki ,  Heung Lak Park ,  Bok Hoen Kim

发明人： Xinhai Han ,  Nagarajan Rajagopalan ,  Ji Ae Park ,  Bencherki Mebarki ,  Heung Lak Park ,  Bok Hoen Kim

IPC分类号： H01L21/8234

CPC分类号： H01L21/0262 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L29/66136 ,  H01L29/868

摘要： Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.

摘要翻译： 描述了在衬底上形成高电流密度垂直p-i-n二极管的方法。 这些方法包括以下步骤：以含有IV族元素的前体和依次暴露于n型掺杂剂前体和p型掺杂剂前体的任一顺序同时组合。 通过在流过含IV族元素的前体的同时减少或消除掺杂剂前体的流动，在n型和p型层之间沉积本征层。 在沉积n型层，本征层和p型层期间，衬底可以驻留在相同的处理室中，并且衬底在相邻层的沉积之间不暴露于大气中。

公开(公告)号：US08563095B2

公开(公告)日：2013-10-22

申请号：US12724396

申请日：2010-03-15

申请人： Nagarajan Rajagopalan ,  Xinhai Han ,  Ryan Yamase ,  Ji Ae Park ,  Shamik Patel ,  Thomas Nowak ,  Zhengjiang “David” Cui ,  Mehul Naik ,  Heung Lak Park ,  Ran Ding ,  Bok Hoen Kim

发明人： Nagarajan Rajagopalan ,  Xinhai Han ,  Ryan Yamase ,  Ji Ae Park ,  Shamik Patel ,  Thomas Nowak ,  Zhengjiang “David” Cui ,  Mehul Naik ,  Heung Lak Park ,  Ran Ding ,  Bok Hoen Kim

IPC分类号： H05H1/24 ,  C23C16/34

CPC分类号： H01L21/02068 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/56 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11827 ,  H01L2224/11831 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1358 ,  H01L2224/13583 ,  H01L2224/13687 ,  H01L2224/742 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.

摘要翻译： 描述了在衬底的特征上形成包括氮化硅的钝化层的方法。 在沉积方法的第一阶段中，将包含含硅气体和含氮气体的介电沉积气体引入工艺区域并通电以沉积氮化硅层。 在第二阶段中，将具有不同于介电沉积气体的组成不同的处理气体引入处理区并通电以处理氮化硅层。 第一和第二阶段可以执行多次。

公开(公告)号：US08283237B2

公开(公告)日：2012-10-09

申请号：US12978129

申请日：2010-12-23

申请人： Nagarajan Rajagopalan ,  Ji Ae Park ,  Ryan Yamase ,  Shamik Patel ,  Thomas Nowak ,  Li-Qun Xia ,  Bok Hoen Kim ,  Ran Ding ,  Jim Baldino ,  Mehul Naik ,  Sesh Ramaswami

发明人： Nagarajan Rajagopalan ,  Ji Ae Park ,  Ryan Yamase ,  Shamik Patel ,  Thomas Nowak ,  Li-Qun Xia ,  Bok Hoen Kim ,  Ran Ding ,  Jim Baldino ,  Mehul Naik ,  Sesh Ramaswami

IPC分类号： H01L21/30 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L24/13 ,  H01L21/02074 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6719 ,  H01L21/6835 ,  H01L21/68792 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/742 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/11452 ,  H01L2224/1182 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/742 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/05042 ,  H01L2924/00

摘要： A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.

摘要翻译： 通过硅通孔的制造方法包括通过使用其间的粘合剂层将硅板的前表面粘合到载体上来形成基板，以暴露硅板的背面。 氮化硅钝化层沉积在衬底的硅板的暴露的背面上。 在硅板中蚀刻多个通孔，通孔包括侧壁和底壁。 金属导体沉积在通孔中以形成多个通硅通孔。

公开(公告)号：US20120164829A1

公开(公告)日：2012-06-28

申请号：US12977060

申请日：2010-12-22

申请人： Nagarajan Rajagopalan ,  Ji Ae Park ,  Ryan Yamase ,  Shamik Patel ,  Thomas Nowak ,  Li-Qun Xia ,  Bok Hoen Kim ,  Ran Ding ,  Jim Baldino ,  Mehul Naik ,  Sesh Ramaswami

发明人： Nagarajan Rajagopalan ,  Ji Ae Park ,  Ryan Yamase ,  Shamik Patel ,  Thomas Nowak ,  Li-Qun Xia ,  Bok Hoen Kim ,  Ran Ding ,  Jim Baldino ,  Mehul Naik ,  Sesh Ramaswami

IPC分类号： H01L21/28

CPC分类号： H01L24/13 ,  H01L21/02074 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6719 ,  H01L21/6835 ,  H01L21/68792 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/742 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/11452 ,  H01L2224/1182 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/742 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/05042 ,  H01L2924/00

摘要： A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.

摘要翻译： 一种硅通孔制造方法包括蚀刻硅板中的多个通孔。 在硅板的表面和通孔的侧壁和底壁上沉积氧化物衬垫。 然后将金属导体沉积在通孔中。 在可与氧化物衬垫同时使用的另一种方案中，氮化硅钝化层沉积在衬底的硅板的暴露后表面上。

公开(公告)号：US08329575B2

公开(公告)日：2012-12-11

申请号：US12977060

申请日：2010-12-22

申请人： Nagarajan Rajagopalan ,  Ji Ae Park ,  Ryan Yamase ,  Shamik Patel ,  Thomas Nowak ,  Li-Qun Xia ,  Bok Hoen Kim ,  Ran Ding ,  Jim Baldino ,  Mehul Naik ,  Sesh Ramaswami

发明人： Nagarajan Rajagopalan ,  Ji Ae Park ,  Ryan Yamase ,  Shamik Patel ,  Thomas Nowak ,  Li-Qun Xia ,  Bok Hoen Kim ,  Ran Ding ,  Jim Baldino ,  Mehul Naik ,  Sesh Ramaswami

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L24/13 ,  H01L21/02074 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6719 ,  H01L21/6835 ,  H01L21/68792 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/742 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/11452 ,  H01L2224/1182 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/742 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/05042 ,  H01L2924/00

摘要： A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.

摘要翻译： 一种硅通孔制造方法包括蚀刻硅板中的多个通孔。 在硅板的表面和通孔的侧壁和底壁上沉积氧化物衬垫。 然后将金属导体沉积在通孔中。 在可与氧化物衬垫同时使用的另一种方案中，氮化硅钝化层沉积在衬底的硅板的暴露后表面上。

公开(公告)号：US20100087062A1

公开(公告)日：2010-04-08

申请号：US12246374

申请日：2008-10-06

申请人： Annamalai Lakshmanan ,  Dante Manalo ,  Nagarajan Rajagopalan ,  Francimar C. Schmitt ,  Bok Hoen Kim

发明人： Annamalai Lakshmanan ,  Dante Manalo ,  Nagarajan Rajagopalan ,  Francimar C. Schmitt ,  Bok Hoen Kim

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/31633 ,  C23C16/0272 ,  C23C16/029 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/76801

摘要： A method and apparatus for depositing organosilicate dielectric layers having good adhesion properties and low dielectric constant. Embodiments are described in which layers are deposited at low temperature and at high temperature. The low temperature layers are generally post-treated, whereas the high temperature layers need no post treating. Adhesion of the layers is promoted by use of an initiation layer.

摘要翻译： 一种用于沉积具有良好粘合性能和低介电常数的有机硅酸盐电介质层的方法和装置。 描述了在低温和高温下沉积层的实施例。 低温层通常经过后处理，而高温层不需要后处理。 通过使用起始层促进层的附着。

公开(公告)号：US07371427B2

公开(公告)日：2008-05-13

申请号：US10442579

申请日：2003-05-20

申请人： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

发明人： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

IPC分类号： B08B9/00 ,  B05D7/22

CPC分类号： H01L21/7684 ,  C23C16/4404 ,  C23G5/00 ,  H01L21/3212 ,  H01L21/76828 ,  H01L21/76838

摘要： Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

摘要翻译： 由于形成覆盖势垒层而在铜层中产生的不希望的小丘可以通过单独或组合优化各种工艺参数而显着降低。 可以控制第一组工艺参数以对其中沉积阻挡层的处理室进行预处理。 可以控制第二组工艺参数，以在阻挡层沉积之前最小化去除CuO期间铜层暴露的能量。 可以控制第三组工艺参数以最小化除去氧化铜后的热预算。

公开(公告)号：US07723228B2

公开(公告)日：2010-05-25

申请号：US10442359

申请日：2003-05-20

申请人： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

发明人： Nagarajan Rajagopalan ,  Meiyee Shek ,  Kegang Huang ,  Bok Hoen Kim ,  Hichem M'saad ,  Thomas Nowak

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/02074 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76828 ,  H01L21/7684

摘要： Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

摘要翻译： 由于形成覆盖势垒层而在铜层中产生的不希望的小丘可以通过单独或组合优化各种工艺参数而显着降低。 可以控制第一组工艺参数以对其中沉积阻挡层的处理室进行预处理。 可以控制第二组工艺参数，以在阻挡层沉积之前最小化去除CuO期间铜层暴露的能量。 可以控制第三组工艺参数以最小化除去氧化铜后的热预算。