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    Lead frame for semiconductor device
    4.
    发明授权
    Lead frame for semiconductor device 有权
    半导体器件引线框架

    公开(公告)号：US09472494B2

    公开(公告)日：2016-10-18

    申请号：US13466717

    申请日：2012-05-08

    申请人： Joon Su Kim ,  Jung Soo Park ,  Gi Jeong Kim

    发明人： Joon Su Kim ,  Jung Soo Park ,  Gi Jeong Kim

    IPC分类号： H01L23/48 ,  H01L23/495

    CPC分类号： H01L23/49582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a lead frame for a semiconductor device, which includes a base layer made of copper, a strike plating layer or a self assembly monolayer (SAM), thereby preventing oxidation of a base layer while simplifying the manufacturing process, reducing the manufacturing costs and reducing a failure ratio. In one embodiment, in the lead frame for a semiconductor device including a die pad and a plurality of leads positioned adjacent to each other around the die pad, the lead frame includes a base layer made of copper; and a first strike plating layer formed on the one or more portions of the surface of the base layer.

    摘要翻译： 提供一种半导体器件的引线框架，其包括由铜制成的基底层，触击镀层或自组装单层（SAM），从而防止了基底层的氧化，同时简化了制造工艺，降低了制造成本和 降低故障率。 在一个实施例中，在用于半导体器件的引线框架中，引线框架包括由铜制成的基极层，所述引线框架包括管芯焊盘和围绕管芯焊盘彼此相邻定位的多个引线， 以及形成在所述基底层的所述表面的所述一个或多个部分上的第一触击镀层。

    Semiconductor device including leadframe with downsets
    5.
    发明授权
    Semiconductor device including leadframe with downsets 有权
    半导体器件包括带底片的引线框架

    公开(公告)号：US08674485B1

    公开(公告)日：2014-03-18

    申请号：US12963431

    申请日：2010-12-08

    申请人： Gi Jeong Kim ,  Jae Yoon Kim ,  Kyu Won Lee

    发明人： Gi Jeong Kim ,  Jae Yoon Kim ,  Kyu Won Lee

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49575 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

    摘要： In one embodiment, a semiconductor package includes a generally planar die paddle or die pad that defines multiple peripheral edge segments, and includes one or more tie bars protruding therefrom. In addition, the semiconductor package includes a plurality of leads, portions of which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body. The one or more tie bars and the plurality of leads include downsets that are sized and oriented relative to each other to facilitate enhanced manufacturing.

    摘要翻译： 在一个实施例中，半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘，并且包括从其突出的一个或多个连接杆。 此外，半导体封装包括多个引线，其多个引线从半导体封装的封装主体的相应侧表面突出。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。 芯片焊盘，引线和半导体管芯的至少一部分被封装体封装。 一个或多个连接杆和多个引线包括相对于彼此定尺寸和定向的下沉，以有助于增强制造。

    Increased capacity semiconductor package
    6.
    发明授权
    Increased capacity semiconductor package 有权
    增加容量的半导体封装

    公开(公告)号：US08184453B1

    公开(公告)日：2012-05-22

    申请号：US12183979

    申请日：2008-07-31

    申请人： Jae Yoon Kim ,  Gi Jeong Kim ,  Myung Soo Moon

    发明人： Jae Yoon Kim ,  Gi Jeong Kim ,  Myung Soo Moon

    IPC分类号： H05K5/02

    CPC分类号： H01L23/49541 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： Disclosed is a lead frame and a semiconductor device including the same. The lead frame is provided with a die pad, and first, second and third lands sequentially arranged on an outer circumferential edge. The lead frame can separate the first and second lands or the die pad and the first land using a plating layer formed on the lead frame as a mask, instead of using a separate mask by etching after the application of the encapsulant. As a result thereof, a plurality of lands can be formed at low cost, in comparison with a conventional method. Additionally, the first, second and third lands are exposed to the outside through a lower portion of an encapsulant, and can be surface mounted on an external device through the first, second and third lands. A plating layer formed on bottom surfaces of the first, second and third lands of the lead frame and a process for separately plating nickel (Ni)/gold (An), Ni/Pd/Au, or tin (Sn) can be omitted so as to easily surface mount the semiconductor device to the external device.

    摘要翻译： 公开了一种引线框架和包括该引线框架的半导体器件。 引线框架设置有管芯焊盘，并且顺序地布置在外周边缘上的第一，第二和第三焊盘。 引线框架可以使用形成在引线框架上的镀层作为掩模来分离第一和第二焊盘或裸片焊盘和第一焊盘，而不是在施加密封剂之后通过蚀刻来使用单独的掩模。 作为其结果，与传统方法相比，可以以低成本形成多个焊盘。 此外，第一，第二和第三焊盘通过密封剂的下部暴露于外部，并且可以通过第一，第二和第三焊盘表面安装在外部设备上。 形成在引线框架的第一，第二和第三焊盘的底面上的镀层以及分别镀镍（Ni）/金（An），​​Ni / Pd / Au或锡（Sn）的工艺可以省略 以便容易地将半导体器件表面安装到外部设备。

    Increased I/O leadframe and semiconductor device including same
    8.
    发明授权
    Increased I/O leadframe and semiconductor device including same 有权
    增加的I / O引线框和包括其的半导体器件

    公开(公告)号：US08432023B1

    公开(公告)日：2013-04-30

    申请号：US13161380

    申请日：2011-06-15

    申请人： Gi Jeong Kim ,  Yeon Ho Choi ,  Wan Jong Kim

    发明人： Gi Jeong Kim ,  Yeon Ho Choi ,  Wan Jong Kim

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

    摘要： In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die paddle and some of the leads being exposed in a common exterior surface of the package body.

    摘要翻译： 根据本发明，提供了包括唯一配置的引线框的半导体封装（例如，QFP封装），其尺寸和配置为使半导体封装中的暴露引线的可用数量最大化。 更具体地，本发明的半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘。 此外，半导体封装包括多个引线。 这些引线中的一些包括暴露的底表面部分，其设置在至少两个同心的行或环中，所述至少两个同心的行或环至少部分地绕过管芯焊盘，其他引线包括从半导体封装的封装主体的相应侧表面突出的部分。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。 芯片焊盘，引线和半导体管芯的至少一部分被封装主体封装，其中裸片焊盘的底表面的至少部分和一些引线暴露在封装主体的公共外表面中 。