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    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR 失效
    半导体存储器件及其方法

    公开(公告)号：US20070171755A1

    公开(公告)日：2007-07-26

    申请号：US11616846

    申请日：2006-12-27

    申请人： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    发明人： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

    摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

    摘要翻译： 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

    Multi-port semiconductor memory device and method for accessing and refreshing the same
    5.
    发明授权
    Multi-port semiconductor memory device and method for accessing and refreshing the same 失效
    多端口半导体存储器件及其访问和刷新方法

    公开(公告)号：US07394711B2

    公开(公告)日：2008-07-01

    申请号：US11616846

    申请日：2006-12-27

    申请人： Chi-Sung Oh ,  Ho-Cheol Lee ,  Nam-Jong Kim

    发明人： Chi-Sung Oh ,  Ho-Cheol Lee ,  Nam-Jong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

    摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

    摘要翻译： 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110093235A1

    公开(公告)日：2011-04-21

    申请号：US12900547

    申请日：2010-10-08

    申请人： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    发明人： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    IPC分类号： G01R31/14 ,  H03L7/00

    CPC分类号： G01R31/2884 ,  G01R31/31726

    摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

    摘要翻译： 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

    Multiprocessor system and method thereof
    8.
    发明授权
    Multiprocessor system and method thereof 有权
    多处理器系统及其方法

    公开(公告)号：US07870326B2

    公开(公告)日：2011-01-11

    申请号：US11819601

    申请日：2007-06-28

    申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    IPC分类号： G06F12/00

    CPC分类号： G06F12/02

    摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

    摘要翻译： 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器 银行通过第一个港口。

    Auto-precharge control circuit in semiconductor memory and method thereof
    9.
    发明申请
    Auto-precharge control circuit in semiconductor memory and method thereof 审中-公开
    半导体存储器中的自动预充电控制电路及其方法

    公开(公告)号：US20080205175A1

    公开(公告)日：2008-08-28

    申请号：US12068280

    申请日：2008-02-05

    申请人： Sang-Kyun Park ,  Ho-Cheol Lee

    发明人： Sang-Kyun Park ,  Ho-Cheol Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4076 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4094 ,  G11C2207/229

    摘要： An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command. The auto-precharge control circuit may include a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal; an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal.

    摘要翻译： 半导体存储器中的自动预充电控制电路及其方法，其中自动预充电起点可以变化。 自动预充电起始点可以响应于至少一个控制信号而变化。 自动预充电起始点可以根据频率和/或延迟信息而变化。 响应于包括时钟频率信息的至少一个控制信号，自动预充电起始点可以变化。 自动预充电起点可以根据从模式寄存器设置命令接收到的等待时间信号而变化。 自动预充电控制电路可以包括用于接收包括时钟频率信息和等待时间信息中的至少一个的写入信号，时钟信号和至少一个控制信号的控制电路，并且输出至少一个路径信号; 自动预充电脉冲信号驱动器，用于接收至少一个路径信号，写入信号和使能信号，并产生自动预充电脉冲信号，所述自动预充电脉冲信号标识自动预充电操作的起始点; 以及自动预充电模式使能电路，用于接收时钟信号，自动预充电命令，有效信号和自动预充电脉冲信号，并产生使能信号。

    Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device
    10.
    发明授权
    Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device 有权
    用于通过半导体存储器件中的块选择信息来控制AIVC的装置和方法

    公开(公告)号：US06928023B2

    公开(公告)日：2005-08-09

    申请号：US10465553

    申请日：2003-06-20

    申请人： Ho-Cheol Lee ,  Jung-Soo Ryoo

    发明人： Ho-Cheol Lee ,  Jung-Soo Ryoo

    IPC分类号： G11C7/00 ,  G11C5/06 ,  G11C5/14 ,  G11C8/12

    CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C8/12

    摘要： A method of controlling a bank voltage (AIVC) through memory block selection information, said method comprising the steps of detecting an array block selection signal of an array block disposed distantly from an AIVC driver in response to an activated memory array block selection signal; and supplying a second bank voltage to a memory bank by driving a normal size driver and an oversize driver when detecting the array block selection signal for the distantly disposed array block.

    摘要翻译： 一种通过存储块选择信息控制存储体电压（AIVC）的方法，所述方法包括以下步骤：响应激活的存储器阵列块选择信号，检测远离AIVC驱动器的阵列块的阵列块选择信号; 以及当检测到用于远处布置的阵列块的阵列块选择信号时，通过驱动正常尺寸的驱动器和超大驱动器，将第二存储体电压提供给存储体。