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    Integrated circuit design verification system
    1.
    发明授权
    Integrated circuit design verification system 有权
    集成电路设计验证系统

    公开(公告)号：US08645897B1

    公开(公告)日：2014-02-04

    申请号：US13735054

    申请日：2013-01-07

    申请人： Nandini ,  Gaurav Gupta ,  Rohit Srivastava

    发明人： Nandini ,  Gaurav Gupta ,  Rohit Srivastava

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F2217/66

    摘要： An integrated circuit (IC) design verification system includes a memory for storing an IC design and a processor in communication with the memory. The IC design includes multiple IP cores and the design verification apparatus includes multiple verification modules. The processor configures a first set of connections between the IP cores and the verification modules based on a first connection database and verifies each IP core independently using the first set of connections. Thereafter, the processor configures a second set of connections between the IP cores and the verification modules based on a second connection database generated based on the first connection database, and verifies the multiple IP cores together using the second set of connections.

    摘要翻译： 集成电路（IC）设计验证系统包括用于存储IC设计的存储器和与存储器通信的处理器。 IC设计包括多个IP核，设计验证装置包括多个验证模块。 处理器基于第一连接数据库配置IP核和验证模块之间的第一组连接，并使用第一组连接独立地验证每个IP核。 此后，处理器基于基于第一连接数据库生成的第二连接数据库来配置IP核和验证模块之间的第二组连接，并且使用第二组连接来验证多个IP内核。

    SYSTEM FOR TESTING IC DESIGN
    2.
    发明申请
    SYSTEM FOR TESTING IC DESIGN 审中-公开
    测试IC设计系统

    公开(公告)号：US20160070846A1

    公开(公告)日：2016-03-10

    申请号：US14481899

    申请日：2014-09-09

    申请人： Nandini ,  Rohit Srivastava

    发明人： Nandini ,  Rohit Srivastava

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5022

    摘要： A method for testing an integrated circuit design exercises the design using a set of simulation signals, and partitions a representation of the design into a first set of active elements and a second set of inactive elements. Only the active elements of the first set are exercised using a second set of simulation signals during verification of the integrated circuit design.

    摘要翻译： 用于测试集成电路设计的方法使用一组模拟信号来执行设计，并将设计的表示分割成第一组有源元件和第二组非活动元件。 在验证集成电路设计期间，仅使用第二组模拟信号来执行第一组的有源元件。

    Valve implanting device
    6.
    发明授权
    Valve implanting device 有权
    阀门植入装置

    公开(公告)号：US06951571B1

    公开(公告)日：2005-10-04

    申请号：US10711703

    申请日：2004-09-30

    申请人： Rohit Srivastava

    发明人： Rohit Srivastava

    IPC分类号： A61F2/06 ,  A61F2/24

    CPC分类号： A61F2/2418 ,  A61F2/243 ,  A61F2/2475 ,  A61F2220/0016 ,  A61F2220/005

    摘要： Disclosed is a valve implanting device comprising a collapsible frame, inner and outer guide wires removably connected to the collapsible frame, and a plurality of valve flaps attached to the collapsible frame. The collapsible frame is inserted into a patient's femoral vein or artery, guided to a deployment position using the guide wires, expanded using the guide wires, and stabilized using the guide wires to manipulate fixating hubs on the collapsible frame. The collapsible frame includes a central hub, a plurality of spokes, fixating hubs, gripping members, and a plurality of valve flaps.

    摘要翻译： 公开了一种瓣膜植入装置，其包括可折叠框架，可拆卸地连接到可折叠框架的内部和外部引导线以及附接到可折叠框架的多个瓣瓣。 将可折叠框架插入到患者的股静脉或动脉中，使用引导线引导到展开位置，并使用导丝进行扩张，并使用导丝进行稳定以操纵可折叠框架上的固定毂。 可折叠框架包括中央轮毂，多个轮辐，固定轮毂，夹紧部件和多个阀瓣。

    System and method for clocking integrated circuit
    7.
    发明授权
    System and method for clocking integrated circuit 有权
    时钟集成电路的系统和方法

    公开(公告)号：US09438217B2

    公开(公告)日：2016-09-06

    申请号：US14337244

    申请日：2014-07-22

    申请人： Narayanan Kannan ,  Rohit Srivastava

    发明人： Narayanan Kannan ,  Rohit Srivastava

    IPC分类号： H03K3/00 ,  H03K5/13 ,  H03K5/135

    CPC分类号： H03K5/131 ,  H03K5/133 ,  H03K5/135

    摘要： A system and method of clocking an integrated circuit (IC) includes determining operating characteristics of the IC. The IC has multiple domains and each domain receives a respective domain clock signal. A skew value is determined for each of the domain clock signals, where each skew value is associated with a respective domain of the IC. The domain clock signals are generated from a reference clock signal and each domain clock signal is skewed from the reference clock according to the respective skew value.

    摘要翻译： 对集成电路（IC）进行计时的系统和方法包括确定IC的工作特性。 IC具有多个域，并且每个域接收相应的域时钟信号。 为每个域时钟信号确定偏斜值，其中每个偏斜值与IC的相应域相关联。 域时钟信号从参考时钟信号产生，并且每个域时钟信号根据相应的偏移值从参考时钟偏斜。

    ARCHITECTURE FOR ENERGY MANAGEMENT OF MULTI CUSTOMER MULTI TIME ZONE DISTRIBUTED FACILITIES
    8.
    发明申请
    ARCHITECTURE FOR ENERGY MANAGEMENT OF MULTI CUSTOMER MULTI TIME ZONE DISTRIBUTED FACILITIES 有权
    多用户多区域分布式设施能源管理体系结构

    公开(公告)号：US20130261833A1

    公开(公告)日：2013-10-03

    申请号：US13593569

    申请日：2012-08-24

    申请人： Ravi Meghani ,  Rohit Srivastava ,  Subhasis Mandal ,  Sudipta Ghosh ,  Anurag Srivastava

    发明人： Ravi Meghani ,  Rohit Srivastava ,  Subhasis Mandal ,  Sudipta Ghosh ,  Anurag Srivastava

    IPC分类号： G06F1/26

    CPC分类号： G06Q50/06 ,  G06Q10/10 ,  Y02P90/84

    摘要： A system and method for energy management for multi customer multi time zone distributed facilities are disclosed. In one embodiment, data associated with the energy management of the multi customer distributed facilities located in different time zones is obtained based on associated energy models by a data acquisition/integration layer. Further, the obtained data for energy management of the multi customer distributed facilities is transformed by a data management layer. Furthermore, control commands are generated using the transformed data and associated one or more pre-defined thresholds and set-points by an energy transaction layer. Also, energy of the multi customer distributed facilities is substantially simultaneously managed using the generated control commands by the energy transaction layer.

    摘要翻译： 公开了一种用于多用户多时区分布式设施的能量管理系统和方法。 在一个实施例中，与位于不同时区的多客户分布式设施的能量管理相关联的数据是通过数据采集/集成层的相关能量模型获得的。 此外，所获得的多客户分布式设施的能量管理数据被数据管理层变换。 此外，使用经变换的数据和由能量事务层相关联的一个或多个预定义的阈值和设定点来生成控制命令。 此外，使用由能量事务层生成的控制命令，基本上同时管理多客户分布式设施的能量。