公开(公告)号：US06449712B1

公开(公告)日：2002-09-10

申请号：US09410851

申请日：1999-10-01

申请人： Naohiko Irie ,  Tony Lee Werner ,  Chih-Jui Peng ,  Sebastian H. Ziesler ,  Jackie A. Freeman ,  Sivaram Krishnan

发明人： Naohiko Irie ,  Tony Lee Werner ,  Chih-Jui Peng ,  Sebastian H. Ziesler ,  Jackie A. Freeman ,  Sivaram Krishnan

IPC分类号： G06F9455

CPC分类号： G06F9/30174 ,  G06F9/30058 ,  G06F9/3842

摘要： A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.

摘要翻译： 构造为执行32位固定长度指令集体系结构的处理器元件向后兼容，用于通过将16位指令中的每一个转换为一个或多个32位的序列来执行16位固定长度指令集架构 说明。 32位指令集架构包括“准备分支”指令，允许在分支之前设置分支指令的目标地址。 组合32位准备到分支和分支指令以执行与16位延迟时隙指令相结合的16位分支指令。

公开(公告)号：US06457118B1

公开(公告)日：2002-09-24

申请号：US09410549

申请日：1999-10-01

申请人： Chih-Jui Peng ,  Glenn Ashley Farrall ,  Sivaram Krishnan

发明人： Chih-Jui Peng ,  Glenn Ashley Farrall ,  Sivaram Krishnan

IPC分类号： G06F938

CPC分类号： G06F9/30167 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838

摘要： According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to the present invention can be operative on a variety of computer architectures, including RISC architectures.

摘要翻译： 根据本发明，提供了用于在流水线架构中设置所选操作数字段的技术。 根据本发明的用于有效选择操作数字段的方法和系统可以在各种计算机体系结构（包括RISC体系结构）上运行。

公开(公告)号：US06393523B1

公开(公告)日：2002-05-21

申请号：US09411452

申请日：1999-10-01

申请人： Chih-Jui Peng ,  Margaret Gearty ,  Naohiko Irie ,  Tony L. Werner

发明人： Chih-Jui Peng ,  Margaret Gearty ,  Naohiko Irie ,  Tony L. Werner

IPC分类号： G06F1200

CPC分类号： G06F9/3812 ,  G06F12/0848 ,  G06F12/0891

摘要： A processor having an execution pipeline and a cache memory including a plurality of cache blocks with instruction words held in selected ones of the cache blocks. An ICBI address buffer is provided for holding addresses of instruction cache blocks to be invalidated by ICBI instructions pending in the processor's execution pipeline. An instruction cache controller coupled to the cache memory generates cache accesses to invalidate specified cache blocks in response to receiving buffered addresses from the ICBI address buffer. Preferably the cache accesses serve to commit ICBI instructions to the instruction cache asynchronously with respect to the processor's execution pipeline.

摘要翻译： 具有执行流水线的处理器和包括多个高速缓存块的高速缓冲存储器，其中指令字被保存在所选择的高速缓存块中。 提供ICBI地址缓冲器，用于保持指令高速缓存块的地址，以使处理器执行流水线中待处理的ICBI指令无效。 耦合到高速缓冲存储器的指令高速缓存控制器响应于从ICBI地址缓冲器接收缓冲的地址而产生高速缓存访​​问以使指定的高速缓存块无效。 优选地，高速缓存访​​问用于相对于处理器的执行管线异步地将ICBI指令提交给指令高速缓存。

公开(公告)号：US06408381B1

公开(公告)日：2002-06-18

申请号：US09410926

申请日：1999-10-01

申请人： Margaret Gearty ,  Chih-Jui Peng

发明人： Margaret Gearty ,  Chih-Jui Peng

IPC分类号： G06F930

CPC分类号： G06F9/30076 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3863 ,  G06F9/3867

摘要： A method for low latency access to the control space. A pipeline processor executes instructions in multiple stages including a decode stage, one or more execution, stages, and a writeback stage. A control space access instruction includes a first field containing a control register specifier and a second field containing a general purpose register specifier. The decode stage is configured to decode the first and second fields and place the decoded contents on a global operand bus. The specified control register is addressed from the global operand bus while the access instruction is in decode. In the case of a read instruction, the addressed control register places its contents on the global operand bus while the instruction remains in decode. In the case of a write instruction, the general purpose register is addressed during the execution stage and its contents placed on the global operand bus during the writeback stage such that the contents of the addressed general purpose register are moved to the addressed configuration register during the writeback stage.

摘要翻译： 用于低延迟访问控制空间的方法。 流水线处理器执行多个阶段的指令，包括解码阶段，一个或多个执行阶段和回写阶段。 控制空间访问指令包括包含控制寄存器说明符的第一字段和包含通用寄存器说​​明符的第二字段。 解码级被配置为对第一和第二字段进行解码，并将解码的内容放置在全局操作数总线上。 当访问指令解码时，指定的控制寄存器从全局操作数总线寻址。 在读取指令的情况下，寻址的控制寄存器将其内容放置在全局操作数总线上，同时指令保持解码。 在写指令的情况下，在执行阶段期间寻址通用寄存器，并且在写回阶段期间将其内容放置在全局操作数总线上，使得寻址的通用寄存器的内容在 回写阶段

公开(公告)号：US5535351A

公开(公告)日：1996-07-09

申请号：US222783

申请日：1994-04-04

申请人： Chih-Jui Peng

发明人： Chih-Jui Peng

IPC分类号： G06F12/10 ,  G11C15/00

CPC分类号： G06F12/1054 ,  G06F12/1027 ,  G06F2212/652

摘要： An address translator (42) with a by-pass circuit (106) translates a received effective address into a real address in a first mode of operation by matching a portion of the effective address and a stored translation tag. The address translator outputs a real address corresponding to the matching translation tag on a plurality of bit lines (BIT LINE). The by-pass circuit connects the input effective address to the bit lines in a second mode of operation. The address translator thereby eliminates the need for a subsequent two-to-one multiplexer.

摘要翻译： 具有旁路电路（106）的地址转换器（42）通过匹配有效地址的一部分和存储的转换标签将接收的有效地址转换为处于第一操作模式的实际地址。 地址转换器在多个位线（BIT LINE）上输出与匹配转换标签相对应的实际地址。 旁路电路在第二操作模式下将输入有效地址连接到位线。 因此，地址转换器消除了对后续的两对多路复用器的需要。

公开(公告)号：US06633971B2

公开(公告)日：2003-10-14

申请号：US09411431

申请日：1999-10-01

申请人： Chih-Jui Peng ,  Lew Chua-Eoan

发明人： Chih-Jui Peng ,  Lew Chua-Eoan

IPC分类号： G06F934

CPC分类号： G06F9/3875 ,  G06F9/3824 ,  G06F9/3826

摘要： A method for forwarding data within a pipeline of a pipelined data processor having a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. The result generated by each execution pipeline stage is selectively coupled to an operand input of one of the execution pipeline stages.

摘要翻译： 一种用于在具有多个执行流水线级的流水线数据处理器的流水线内转发数据的方法，其中每个级接受多个操作数输入并产生结果。 每个执行流水线阶段生成的结果选择性地耦合到执行流水线阶段之一的操作数输入。

公开(公告)号：US5682495A

公开(公告)日：1997-10-28

申请号：US353007

申请日：1994-12-09

申请人： Brad B. Beavers ,  Lew Chua-Eoan ,  Pei-Chun Peter Liu ,  Chih-Jui Peng

发明人： Brad B. Beavers ,  Lew Chua-Eoan ,  Pei-Chun Peter Liu ,  Chih-Jui Peng

IPC分类号： G06F12/10

CPC分类号： G06F12/1036

摘要： A fully associative address translator which includes a number of entries, each of said number of entries translating a received effective address into a real address, each received effective address including a segment identifier and a page identifier. Each of the entries within the fully associative address translator includes a first translation from an effective address segment identifier into a virtual address segment identifier and a second translation from a virtual address page identifier to a real address page identifier. A first valid bit cell is provided for storing a validity bit which indicates the validity of the first translation from the effective address segment identifier to the virtual address segment identifier and a second valid bit cell is also provided for storing a validity bit indicating the validity of the second translation from the virtual address page identifier to the real address page identifier wherein a process context switch will invalidate only a portion of each of the entries, thereby reducing the miss penalty associated with a context switch.

摘要翻译： 一种完全关联地址转换器，其包括多个条目，所述数量的条目中的每一个将接收的有效地址转换为实际地址，每个接收到的有效地址包括段标识符和页面标识符。 完全关联地址转译器中的每个条目包括从有效地址段标识符到虚拟地址段标识符的第一转换和从虚拟地址页标识符到真实地址页标识符的第二转换。 提供第一有效比特单元，用于存储指示从有效地址段标识符到虚拟地址段标识符的第一翻译的有效性的有效位，并且还提供第二有效位单元，用于存储指示有效位的有效位 从虚拟地址页标识符到实际地址页标识符的第二转换，其中处理上下文切换将仅使每个条目的一部分无效，从而减少与上下文切换相关联的未命中。

公开(公告)号：US06542983B1

公开(公告)日：2003-04-01

申请号：US09410925

申请日：1999-10-01

申请人： Margaret Rose Gearty ,  Chih-Jui Peng

发明人： Margaret Rose Gearty ,  Chih-Jui Peng

IPC分类号： G06F900

CPC分类号： G06F9/3875 ,  G06F9/3867 ,  G06F9/3877

摘要： In a computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline including a CPU decoder pipestage and the FPU execution pipeline including an FPU decoder pipestage, the method including the steps of, (a) sending a first instruction to the CPU decoder pipestage, (b) sending the first instruction to the FPU decoder pipestage, (c) generating a signal indicating that the first instruction has been accepted by the CPU decoder pipestage, (d) generating a signal indicating that the first instruction has been accepted by the FPU decoder pipestage, (e) sending a second instruction to the CPU decoder pipestage in response to step (d), and (f) sending a second instruction to the FPU decoder pipestage in response to step (c). A corresponding apparatus is also provided.

摘要翻译： 在具有中央处理单元（CPU）执行流水线和浮点单元（FPU）执行流水线的计算机系统中，CPU执行流水线包括CPU解码器管道和包括FPU解码器管道的FPU执行流水线，该方法包括步骤 （a）向CPU解码器分支发送第一指令，（b）将第一指令发送到FPU解码器分支，（c）产生指示第一指令已被CPU解码器分支接收的信号，（d 产生指示第一指令已被FPU解码器分支接收的信号，（e）响应于步骤（d）向CPU解码器分支发送第二指令，以及（f）向FPU解码器发送第二指令 响应于步骤（c）的分支。 还提供了相应的装置。

公开(公告)号：US5530822A

公开(公告)日：1996-06-25

申请号：US223067

申请日：1994-04-04

申请人： Brad Beavers ,  Lew Chua-Eoan ,  Chih-Jui Peng

发明人： Brad Beavers ,  Lew Chua-Eoan ,  Chih-Jui Peng

IPC分类号： G06F12/10 ,  G11C15/00

CPC分类号： G06F12/1036

摘要： An address translator (126) translates addresses, acting like a register file or a table, as necessary. The address translator contains a number of entries for matching an input address to a stored tag. An entry outputs a stored translated address if its stored tag matches the input address. A decoder (138) selects a particular entry in which to store an input translated address when the address translator operates as a register file. In these cases, a register number is also stored in the particular entry's as the entry's tag. Later, when it is necessary to read the particular entry, the register number is compared to each entry's tag to find a match. The disclosed address translator is compatible with both hardware and software refill algorithms ("tablewalks") without impacting its critical read speed path.

摘要翻译： 地址转换器（126）根据需要翻译地址，像寄存器文件或表格一样。 地址转换器包含一些用于将输入地址与存储标签进行匹配的条目。 如果存储的标签与输入地址匹配，则输入输出存储的翻译地址。 当地址转换器作为寄存器文件操作时，解码器（138）选择存储输入转换地址的特定条目。 在这些情况下，寄存器编号也作为条目的标签存储在特定条目中。 稍后，当需要读取特定条目时，将寄存器编号与每个条目的标签进行比较以找到匹配项。 所公开的地址转换器与硬件和软件补充算法（“台式”）兼容，而不影响其关键的读取速度路径。

公开(公告)号：US5604879A

公开(公告)日：1997-02-18

申请号：US653677

申请日：1996-05-23

申请人： Brad Beavers ,  Chua-Eoan Lew ,  Pei-Chun Liu ,  Chih-Jui Peng

发明人： Brad Beavers ,  Chua-Eoan Lew ,  Pei-Chun Liu ,  Chih-Jui Peng

IPC分类号： G06F12/10

CPC分类号： G06F12/1036

摘要： A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) that independently compare an input segment identifier and an input page identifier to a stored segment identifier and a stored page identifier, respectively. The ERAT outputs a stored real address field (DATA) associated with a stored segment-stored page pair if both comparisons are equivalent. The ERAT can invalidate stored translations on the basis of segment or page granularity by requiring either a segment or a page CAM field match, respectively, during an invalidate operation.

摘要翻译： CAM / SRAM结构（44）执行与分段/寻呼寻址方案兼容但仅需要单个查找步骤的地址转换。 有效到实地址转换器（ERAT）中的每个条目具有分别独立地将输入段标识符和输入页标识符与存储的段标识符和存储的页标识符进行独立比较的两个CAM字段（ESID，EPI）。 如果两个比较是等效的，ERAT输出与存储的段存储的页对相关联的存储的实际地址字段（DATA）。 在无效操作期间，ERAT可以通过分别要求分段或页面CAM字段匹配来使分段或页面粒度的存储转换无效。