公开(公告)号：US20050263802A1

公开(公告)日：2005-12-01

申请号：US11129439

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。 低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。 包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

公开(公告)号：US07238996B2

公开(公告)日：2007-07-03

申请号：US11129439

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

IPC分类号： H01L29/70

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。 低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。 包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

公开(公告)号：US07759744B2

公开(公告)日：2010-07-20

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62 ,  H01L27/10 ,  H01L29/73

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，在硅衬底102上包括第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数膜的P型MOSFET 120 12和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。第一 高介电常数膜111和第二高介电常数膜112含有选自Hf和Zr的一种或多种元素。

公开(公告)号：US20050253181A1

公开(公告)日：2005-11-17

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L31/119

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数的P型MOSFET 120 膜112和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。 第一高介电常数膜111和第二高介电常数膜112包含从由Hf和Zr组成的组中选择的一种或多种元素。

公开(公告)号：US20060043497A1

公开(公告)日：2006-03-02

申请号：US11210873

申请日：2005-08-25

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto

IPC分类号： H01L29/76

CPC分类号： H01L29/518 ,  H01L21/0214 ,  H01L21/02142 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/28185 ,  H01L21/28238 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/1033

摘要： Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor device 100 has a silicon substrate 101 and a P-type MOSFET 103 comprising a SiON film 113 formed on the silicon substrate 101, and a polycrystalline silicon film 106. Any one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon film 106 and the SiON film 113, and concentration of the metal(s) at the interface 115 is adjusted to 5×1013 atoms/cm2 or more and less than 1.4×1015 atoms/cm2.

摘要翻译： 与仅通过将杂质掺杂到沟道区域中的阈值电压的常规调节相比，场效应晶体管的阈值电压被成功地用较小剂量的杂质调节。 半导体器件100具有硅衬底101和包括形成在硅衬底101上的SiON膜113的P型MOSFET 103和多晶硅膜106.选自以下的金属中的任何一种或两种以上选自 的Hf，Zr，Al，La，Pr，Y，Ti，Ta和W被放置在多晶硅膜106和SiON膜113之间的界面115处，并且界面115处的金属的浓度 被调整到5×10 13原子/ cm 2以上且小于1.4×10 15原子/ cm 2以上。

公开(公告)号：US07754570B2

公开(公告)日：2010-07-13

申请号：US11210873

申请日：2005-08-25

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto

IPC分类号： H01L21/336

CPC分类号： H01L29/518 ,  H01L21/0214 ,  H01L21/02142 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/28185 ,  H01L21/28238 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/1033

摘要： Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor device 100 has a silicon substrate 101 and a P-type MOSFET 103 comprising a SiON film 113 formed on the silicon substrate 101, and a polycrystalline silicon film 106. Any one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon film 106 and the SiON film 113, and concentration of the metal(s) at the interface 115 is adjusted to 5×1013 atoms/cm2 or more and less than 1.4×1015 atoms/cm2.

摘要翻译： 与仅通过将杂质掺杂到沟道区域中的阈值电压的常规调节相比，场效应晶体管的阈值电压被成功地用较小剂量的杂质调节。 半导体器件100具有硅衬底101和包括形成在硅衬底101上的SiON膜113的P型MOSFET 103和多晶硅膜106.选自以下的金属中的任何一种或两种以上选自 的Hf，Zr，Al，La，Pr，Y，Ti，Ta和W被放置在多晶硅膜106和SiON膜113之间的界面115处，并且界面115处的金属的浓度 调整为5×1013原子/ cm 2以上且小于1.4×1015原子/ cm 2。

公开(公告)号：US20060145265A1

公开(公告)日：2006-07-06

申请号：US11300419

申请日：2005-12-15

申请人： Yuri Masuoka ,  Naohiko Kimizuka ,  Kiyotaka Imai ,  Toshiyuki Iwamoto

发明人： Yuri Masuoka ,  Naohiko Kimizuka ,  Kiyotaka Imai ,  Toshiyuki Iwamoto

IPC分类号： H01L29/94

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： While forming an N-type MOSFET 118 and a P-type MOSFET 120 within regions operating using the same power supply voltage, thickness of a gate insulating film 106a of an N-type MOSFET 118 is made to be thicker than thickness of a gate insulating film 106b of a P-type MOSFET 120.

摘要翻译： 在使用相同电源电压工作的区域内形成N型MOSFET 118和P型MOSFET 120时，使N型MOSFET118的栅极绝缘膜106a的厚度比栅极厚度厚 P型MOSFET120的绝缘膜106b。

公开(公告)号：US20080203500A1

公开(公告)日：2008-08-28

申请号：US12071126

申请日：2008-02-15

申请人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

发明人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

IPC分类号： H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/78

摘要： A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.

摘要翻译： 一种设置有MIS型场效应晶体管的半导体器件，包括硅衬底，具有通过含硅绝缘膜形成在硅衬底上的高介电常数金属氧化物膜的栅极绝缘膜，含硅栅电极 形成在所述栅极绝缘膜上的侧壁，以及在所述栅电极的侧面上包含氧化硅作为构成材料的侧壁，其中，所述侧壁与所述栅电极的至少所述侧面之间插入有氮化硅膜。 该半导体器件尽管具有栅极长度小的精细结构，但能够实现低功耗和快速操作。

公开(公告)号：US20060131670A1

公开(公告)日：2006-06-22

申请号：US10561608

申请日：2004-04-26

申请人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

发明人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

IPC分类号： H01L29/76

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/78

摘要： A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.

摘要翻译： 一种设置有MIS型场效应晶体管的半导体器件，包括硅衬底，具有通过含硅绝缘膜形成在硅衬底上的高介电常数金属氧化物膜的栅极绝缘膜，含硅栅电极 形成在所述栅极绝缘膜上的侧壁，以及在所述栅电极的侧面上包含氧化硅作为构成材料的侧壁，其中，所述侧壁与所述栅电极的至少所述侧面之间插入有氮化硅膜。 该半导体器件尽管具有栅极长度小的精细结构，但能够实现低功耗和快速操作。

公开(公告)号：US20120315736A1

公开(公告)日：2012-12-13

申请号：US13585394

申请日：2012-08-14

申请人： Toshiyuki Iwamoto ,  Gen Tsutsui

发明人： Toshiyuki Iwamoto ,  Gen Tsutsui

IPC分类号： H01L21/336

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823462

摘要： A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region, forming second extension regions in the second region using the second gate electrode as a mask, forming first side walls and second side walls on side surfaces of the first gate electrode and on side surfaces of the second gate electrode, respectively, and forming a source and a drain of the FinFET in the first region using the first gate electrode and first side walls as masks and forming a source and a drain of the PlanarFET in the second region by an ion implantation method using the second gate electrode and second side walls as masks, at the same time.

摘要翻译： 一种制造半导体器件的方法包括：形成包括FinFET（Fin场效应晶体管）的第一区域，形成包括平面场效应晶体管的平面场效应晶体管的平面场效应晶体管的第二区域，形成第一区域中的多个鳍片的第一延伸区域; 使用所述第二栅电极作为掩模在所述第二区域中形成第二延伸区域，分别在所述第一栅电极的侧表面和所述第二栅电极的侧表面上分别形成第一侧壁和第二侧壁，以及形成源 使用第一栅电极和第一侧壁作为掩模在第一区域中的FinFET的漏极，并且通过使用第二栅电极和第二侧壁作为掩模的离子注入方法在第二区域中形成平面FET的源极和漏极 ， 与此同时。