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15 条记录 (耗时 0.02 秒)

    Reception circuit
    1.
    发明授权
    Reception circuit 有权
    接收电路

    公开(公告)号：US08681913B2

    公开(公告)日：2014-03-25

    申请号：US13295052

    申请日：2011-11-12

    申请人： Naohisa Takayama ,  Ryoji Hayashi ,  Hiroyuki Joba ,  Morishige Hieda

    发明人： Naohisa Takayama ,  Ryoji Hayashi ,  Hiroyuki Joba ,  Morishige Hieda

    IPC分类号： H03D1/00

    CPC分类号： H04L7/042

    摘要： A reception circuit is provided which can detect the beginning of data regardless of a preamble or a unique word contained or not in a received signal and regardless of coding systems for received signals. The reception circuit includes a correlation operation portion that performs a correlation operation to generate a correlation signal while sliding one symbol of reference signal in relation to a received signal. The reference signal goes to a high level during a first half symbol period and goes to a low level during a second half symbol period. The reception circuit further includes: a delay portion that outputs a delay signal by delaying the received signal for a half symbol period in relation to the received signal; and a data beginning timing detection portion that detects a beginning peak timing for the correlation signal as a beginning timing of data contained in the delay signal.

    摘要翻译： 提供了一种可以检测数据开始的接收电路，而不管前置码或包含或不包含在接收信号中的唯一字，而不管接收信号的编码系统如何。 接收电路包括相关操作部分，其执行相关操作以产生相关信号，同时相对于接收信号滑动参考信号的一个符号。 参考信号在第一半符号周期期间进入高电平，并且在后半个符号周期期间变为低电平。 接收电路还包括：延迟部分，通过相对于所接收的信号延迟接收信号半个符号周期来输出延迟信号; 以及数据开始定时检测部分，其将相关信号的开始峰值定时检测为包含在延迟信号中的数据的开始定时。

    RECEPTION CIRCUIT
    2.
    发明申请
    RECEPTION CIRCUIT 有权
    接收电路

    公开(公告)号：US20120128106A1

    公开(公告)日：2012-05-24

    申请号：US13295052

    申请日：2011-11-12

    申请人： Naohisa TAKAYAMA ,  Ryoji Hayashi ,  Hiroyuki Joba ,  Morishige Hieda

    发明人： Naohisa TAKAYAMA ,  Ryoji Hayashi ,  Hiroyuki Joba ,  Morishige Hieda

    IPC分类号： H04L27/06

    CPC分类号： H04L7/042

    摘要： A reception circuit is provided which can detect the beginning of data regardless of a preamble or a unique word contained or not in a received signal and regardless of coding systems for received signals. The reception circuit includes a correlation operation portion that performs a correlation operation to generate a correlation signal while sliding one symbol of reference signal in relation to a received signal. The reference signal goes to a high level during a first half symbol period and goes to a low level during a second half symbol period. The reception circuit further includes: a delay portion that outputs a delay signal by delaying the reference signal for a half symbol period in relation to the received signal; and a data beginning timing detection portion that detects a beginning peak timing for the correlation signal as a beginning timing of data contained in the delay signal.

    摘要翻译： 提供了一种可以检测数据开始的接收电路，而不管前置码或包含或不包含在接收信号中的唯一字，而不管接收信号的编码系统如何。 接收电路包括相关操作部分，其执行相关操作以产生相关信号，同时相对于接收信号滑动参考信号的一个符号。 参考信号在第一半符号周期期间进入高电平，并且在后半个符号周期期间变为低电平。 接收电路还包括：延迟部分，通过相对于所接收的信号将参考信号延迟半符号周期来输出延迟信号; 以及数据开始定时检测部分，其将相关信号的开始峰值定时检测为包含在延迟信号中的数据的开始定时。

    Mixer circuit
    8.
    发明授权
    Mixer circuit 失效
    搅拌机电路

    公开(公告)号：US06759887B2

    公开(公告)日：2004-07-06

    申请号：US10450819

    申请日：2003-06-18

    申请人： Yoshinori Takahashi ,  Hiroyuki Joba

    发明人： Yoshinori Takahashi ,  Hiroyuki Joba

    IPC分类号： G06F744

    CPC分类号： H03D7/1425 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0025

    摘要： A mixer circuit includes a local frequency multiplication unit including a pair of transistors having bases receiving local oscillation waves inverted in phase. A reference transistor is differentially connected with the pair of transistors. The pair of transistors and the reference transistor have their emitters connected to a collector of a modulated wave input transistor having a base receiving a modulated wave signal and an emitter connected to a constant current source, and have their collectors connected to a load. The commonly connected collectors of the pair of transistors and the collector of the reference transistor output modulation signals inverted in phase. The sum of currents flowing through the pair of transistors and the reference transistor equals the constant current of the constant current source flowing through the modulated wave input transistor, and the mixer circuit has a gain.

    摘要翻译： 混频器电路包括本地倍频单元，其包括具有接收相位反转的本地振荡波的基极对的一对晶体管。 参考晶体管与该对晶体管差分连接。 一对晶体管和参考晶体管的发射极连接到具有接收调制波信号的基极和连接到恒定电流源的发射极的调制波输入晶体管的集电极，并且使它们的集电极连接到负载。 一对晶体管的共同连接的集电极和参考晶体管的集电极输出调制信号同相反相。 流过该对晶体管和参考晶体管的电流的总和等于流经调制波输入晶体管的恒流源的恒定电流，并且混频器电路具有增益。

    High-frequency amplifier
    10.
    发明授权
    High-frequency amplifier 失效
    高频放大器

    公开(公告)号：US06750720B1

    公开(公告)日：2004-06-15

    申请号：US10149390

    申请日：2002-06-12

    申请人： Kazutomi Mori ,  Shintarou Shinjo ,  Hiroyuki Joba ,  Yoshinori Takahashi ,  Yukio Ikeda ,  Tadashi Takagi

    发明人： Kazutomi Mori ,  Shintarou Shinjo ,  Hiroyuki Joba ,  Yoshinori Takahashi ,  Yukio Ikeda ,  Tadashi Takagi

    IPC分类号： H03F304

    CPC分类号： H03F1/0261 ,  H03F1/302 ,  H03F3/19 ,  H03F3/343

    摘要： Between resistors 13, 14 and an NPN bipolar transistor 12 are interposed PNP bipolar transistors 21, 22 forming a current mirror 20 that uses a collector current of the NPN bipolar transistor 12 as a reference current, and determines a collector current of an NPN bipolar transistor 11. This makes possible to design a size ratio A of the PNP bipolar transistors 21, 22 so as to approximate a voltage drop &Dgr;Vb to a value close to zero, and to suppress the voltage drop &Dgr;Vb of the base voltage Vb accordingly to achieve a high power output and high efficiency when a high frequency input signal Pin increases and generates a base rectified current.

    摘要翻译： 在电阻器13,14和NPN双极晶体管12之间插入形成使用NPN双极晶体管12的集电极电流作为参考电流的电流镜20的PNP双极晶体管21,22，并且确定NPN双极晶体管的集电极电流 这使得可以设计PNP双极晶体管21,22的尺寸比A，以将电压降ΔVV近似为接近于零的值，并且相应地抑制基极电压Vb的电压降DeltaVb以实现 当高频输入信号Pin增加并产生基极整流电流时，高功率输出和高效率。