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公开(公告)号：US20100017585A1
公开(公告)日：2010-01-21
申请号：US12585781
申请日：2009-09-24
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译： 一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作 定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。 指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。 当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。
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2.发明申请公开(公告)号：US20060155976A1
公开(公告)日：2006-07-13
申请号：US11312830
申请日：2005-12-21
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/3842 , G06F9/3861
摘要： A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgement instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgement instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgement instruction.
摘要翻译： 微型计算机包括能够在并行分时操作中执行多个任务的CPU。 这些任务包括至少一个具有固定循环程序的特殊任务，其具有指令地址的不断增加。 当CPU在特殊任务中执行条件判断指令时，CPU在不需要执行特殊操作中描述的指令的情况下禁止将CPU和外围电路两者的条件判断指令的执行结果反映 条件判决指示后的任务。
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公开(公告)号：US20060161763A1
公开(公告)日：2006-07-20
申请号：US11330237
申请日：2006-01-12
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译： 一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作 定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。 指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。 当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。
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4.发明授权Microcomputer and encoding system for executing peripheral function instructions 有权用于执行外围功能指令的微机和编码系统公开(公告)号：US07991982B2
公开(公告)日：2011-08-02
申请号：US12585781
申请日：2009-09-24
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译： 一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作 定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。 指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。 当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。
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5.发明授权公开(公告)号：US07725694B2
公开(公告)日：2010-05-25
申请号：US11312830
申请日：2005-12-21
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3842 , G06F9/3861
摘要： A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.
摘要翻译： 微型计算机包括能够在并行分时操作中执行多个任务的CPU。 这些任务包括至少一个具有固定循环程序的特殊任务，其具有指令地址的不断增加。 当CPU在特殊任务中执行条件判断指令时，CPU在不需要执行特殊操作中描述的指令的情况下禁止将CPU和外围电路两者的条件判断指令的执行结果反映 条件判决指示后的任务。
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6.发明授权Microcomputer with mode decoder operable upon receipt of either power-on or external reset signal 有权具有模式解码器的微计算机，在接收到电源接通或外部复位信号时可操作公开(公告)号：US07467294B2
公开(公告)日：2008-12-16
申请号：US11270447
申请日：2005-11-10
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译： 微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。 多个操作模式选择端子被设计为可用作通用输入端子或输出端子。 解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。 定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。 当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。
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公开(公告)号：US20060107082A1
公开(公告)日：2006-05-18
申请号：US11270447
申请日：2005-11-10
IPC分类号： G06F1/30
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译： 微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。 多个操作模式选择端子被设计为可用作通用输入端子或输出端子。 解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。 定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。 当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。
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8.发明授权Semiconductor integrated circuit having multiple semiconductor chips with signal terminals 有权具有多个具有信号端子的半导体芯片的半导体集成电路公开(公告)号：US07466159B2
公开(公告)日：2008-12-16
申请号：US11586560
申请日：2006-10-26
IPC分类号： G01R31/02
CPC分类号： G11C5/066 , G01R31/31926 , G11C29/1201 , G11C29/48 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes: a package; semiconductor chips in the package including a signal terminal; and a wiring connecting signal terminals. One semiconductor chip is a test object chip including a probe terminal and a test object terminal. The probe terminal connects to an external terminal for testing the test object terminal. The test object chip further includes: a common wiring for connecting the probe terminal and the test object terminal; a first switch for connecting/disconnecting the probe terminal and the common wiring; a second switch for connecting/disconnecting the test object terminal and the common wiring; and a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal.
摘要翻译： 半导体集成电路包括：封装; 封装中的半导体芯片包括信号端子; 和连接信号端子的接线。 一个半导体芯片是包括探针端子和测试对象端子的测试对象芯片。 探头端子连接到外部端子，用于测试对象端子。 测试对象芯片还包括：用于连接探针端子和测试对象端子的公共布线; 用于连接/断开探针端子和公共布线的第一开关; 用于连接/断开测试对象端子和公共布线的第二开关; 以及用于中断要输入到探头端子的输入电路的测试信号的测试信号中断元件。
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公开(公告)号：US20050188131A1
公开(公告)日：2005-08-25
申请号：US11007298
申请日：2004-12-09
CPC分类号： G06F13/24
摘要： A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.
摘要翻译： 单片微计算机包括逻辑电路，CPU和触发器，用于基于时钟信号将由逻辑电路提供的中断请求信号同步到CPU。 多芯片仿真装置包括分别用于仿真逻辑电路，CPU和触发器的功能的外围评估芯片，CPU评估芯片和装置。 当在开发中使用多芯片仿真装置来模拟单片机的功能时，用于模拟触发器的功能的装置同步中断请求信号以吸收由中断请求信号引起的延迟时间 由于外围评估芯片和CPU评估芯片之间的物理距离，使得仿真中的中断处理定时与单片机的实际操作中的中断处理定时相匹配。
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公开(公告)号：US07890737B2
公开(公告)日：2011-02-15
申请号：US12155017
申请日：2008-05-29
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： A microcomputer for functioning according to operation modes includes; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.
摘要翻译： 根据操作模式起作用的微型计算机包括： 模式计数器，其对施加到模式设置终端的信号中的电平变化次数进行计数; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。 在测试模式下，能够从外部电路输入测试指令数据。
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