公开(公告)号：US06611728B1

公开(公告)日：2003-08-26

申请号：US09389230

申请日：1999-09-03

申请人： Natsuyo Morioka ,  Hisafumi Iwata ,  Junko Konishi ,  Yoko Ikeda ,  Kazunori Nemoto ,  Makoto Ono ,  Yasuhiro Yoshitake

发明人： Natsuyo Morioka ,  Hisafumi Iwata ,  Junko Konishi ,  Yoko Ikeda ,  Kazunori Nemoto ,  Makoto Ono ,  Yasuhiro Yoshitake

IPC分类号： G06F1900

CPC分类号： G01N21/9501 ,  H01L22/12 ,  H01L22/20

摘要： An inspection system comprises an inspection machine for inspecting a work which is processed in one of the manufacturing processes of a manufacturing line and an analysis system for outputting an inspection history list obtained by making calculations from the inspected result. The inspection history list shows a matrix of first information as the inspection processes in which the work is inspected or the manufacturing processes corresponding to the inspection processes in which the work is inspected and second information as to the works inspected by the inspection machine.

摘要翻译： 检查系统包括检查机器，用于检查在生产线的一个制造过程中处理的工件和用于输出通过从检查结果进行计算而获得的检查履历表的分析系统。 检查历史列表显示作为检查工作的检查过程的第一信息矩阵或与检查工作相关的检查过程对应的制造过程以及由检查机检查的工件的第二信息。

公开(公告)号：US06539272B1

公开(公告)日：2003-03-25

申请号：US09494939

申请日：2000-02-01

申请人： Makoto Ono ,  Hisafumi Iwata ,  Kazunori Nemoto

发明人： Makoto Ono ,  Hisafumi Iwata ,  Kazunori Nemoto

IPC分类号： G06F1900

CPC分类号： G01N21/956 ,  G01N21/47 ,  G01N21/94 ,  G01N21/9501

摘要： An analysis method includes one or more inspection steps for inspecting defects on a wafer, including an electrical inspection an step for inspecting electrical function of dies of the wafer, a determination step for determining whether each die is a good die or a bad die by using results obtained in the electrical inspection step, a calculation step for calculating the yield of dies without defects by using results obtained in the determination step, and an output step for outputting a result of the calculation step.

摘要翻译： 分析方法包括检查晶片上的缺陷的一个或多个检查步骤，包括电检查用于检查晶片的管芯的电功能的步骤，用于通过使用用于确定每个管芯是否为良好管芯或坏死的确定步骤 在电检查步骤中获得的结果，通过使用在确定步骤中获得的结果来计算没有缺陷的管芯的产量的计算步骤以及用于输出计算步骤的结果的输出步骤。

公开(公告)号：US08831899B2

公开(公告)日：2014-09-09

申请号：US13127051

申请日：2009-10-15

申请人： Kazunori Nemoto ,  Akira Hamamatsu ,  Hideo Ota ,  Kenji Oka ,  Takahiro Jingu

发明人： Kazunori Nemoto ,  Akira Hamamatsu ,  Hideo Ota ,  Kenji Oka ,  Takahiro Jingu

IPC分类号： G01C19/00 ,  G01N21/00 ,  B82Y35/00 ,  G01N21/93 ,  G01B11/30 ,  G01N21/95 ,  G01N21/88 ,  H01L21/66

CPC分类号： G01B11/303 ,  B82Y35/00 ,  G01N21/93 ,  G01N21/9501 ,  G01N2021/8822 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for determining measurement results of a dark-field inspection apparatus up to a microscopic area. A dark-field inspection apparatus is calibrated using a reference wafer having microroughness of an irregular asperity pattern accurately formed on a surface, and the microroughness of the surface having an ensured microroughness degree. This microroughness is measured by using an AFM, and an expected haze value is obtained based on the measured value. Then, haze of the surface of the reference wafer is measured by the dark-field inspection apparatus to be inspected to obtain an actually-measured haze value, and a difference between the expected haze value and the actually-measured haze value is obtained. Based on this difference, a haze measurement parameter of the dark-field inspection apparatus is adjusted so that the actually-measured haze value and the expected haze value match each other.

摘要翻译： 用于确定暗视场检查装置的测量结果直到微观区域的系统和方法。 使用具有精确形成在表面上的不规则凹凸图案的微粗糙度的参考晶片校准暗场检查装置，并且具有确保的微粗糙度的表面的微粗糙度。 通过使用AFM测量该微粗糙度，并且基于测量值获得预期雾度值。 然后，通过需要检查的暗视野检查装置测量参考晶片的表面的雾度，以获得实际测得的雾度值，并获得预期雾度值和实际测得的雾度值之间的差。 基于该差异，调整暗场检查装置的雾度测量参数，使得实际测量的雾度值和预期雾度值彼此匹配。

公开(公告)号：US20110276299A1

公开(公告)日：2011-11-10

申请号：US13127051

申请日：2009-10-15

申请人： Kazunori Nemoto ,  Akira Hamamatsu ,  Hideo Ota ,  Kenji Oka ,  Takahiro Jingu

发明人： Kazunori Nemoto ,  Akira Hamamatsu ,  Hideo Ota ,  Kenji Oka ,  Takahiro Jingu

IPC分类号： G06F19/00

CPC分类号： G01B11/303 ,  B82Y35/00 ,  G01N21/93 ,  G01N21/9501 ,  G01N2021/8822 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technology capable of ensuring measurement results of a dark-field inspection apparatus up to a microscopic area is provided. A dark-field inspection apparatus is calibrated using a bulk wafer as a reference wafer, the bulk wafer having microroughness of an irregular asperity pattern accurately formed on a surface, and the microroughness of the surface having an ensured microroughness degree. The microroughness can be more accurately formed by a chemical treatment with a chemical solution. This microroughness is measured by using an AFM, and an expected haze value is obtained based on the measured value. Then, haze of the surface of the reference wafer is measured by the dark-field inspection apparatus to be inspected to obtain an actually-measured haze value, and a difference between the expected haze value and the actually-measured haze value is obtained. Based on this difference, a haze measurement parameter of the dark-field inspection apparatus is adjusted so that the actually-measured haze value and the expected haze value match each other.

摘要翻译： 提供了一种能够确保暗视场检测装置到微观区域的测量结果的技术。 使用体晶片作为参考晶片校准暗视场检查装置，该体晶片具有精确地形成在表面上的不规则凹凸图案的微粗糙度，并且具有确保的微粗糙度的表面的微粗糙度。 通过化学溶液的化学处理可以更精确地形成微粗糙度。 通过使用AFM测量该微粗糙度，并且基于测量值获得预期雾度值。 然后，通过需要检查的暗视野检查装置测量参考晶片的表面的雾度，以获得实际测得的雾度值，并获得预期雾度值和实际测得的雾度值之间的差。 基于该差异，调整暗场检查装置的雾度测量参数，使得实际测量的雾度值和预期雾度值彼此匹配。

公开(公告)号：US20050233554A1

公开(公告)日：2005-10-20

申请号：US11108736

申请日：2005-04-19

申请人： Toshihito Tsuga ,  Hirohiko Yamamoto ,  Michimasa Funabashi ,  Kazunori Nemoto

发明人： Toshihito Tsuga ,  Hirohiko Yamamoto ,  Michimasa Funabashi ,  Kazunori Nemoto

IPC分类号： H01L21/31 ,  H01L21/20 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/02164 ,  H01L21/02282 ,  H01L21/28035 ,  H01L21/3165 ,  H01L21/84 ,  H01L27/12 ,  H01L29/42324

摘要： The present invention provides a technology for suppressing occurrence of abnormality on a surface of a silicon film other than a single crystal film formed on a wafer. A silicon film is formed on a wafer in step S1 and an oxide film functioning as an abnormality suppression film for suppressing the surface abnormality is formed on the silicon surface on the wafer formed in step S10. The abnormality suppression film is formed by the surface oxidation of the polycrystalline silicon using chemical solution such as ozone water or hydrogen peroxide solution. After forming the abnormality suppression film on the silicon surface, the abnormality suppression film, for example, an abnormal growth suppression film is removed according to need, and then the process of patterning the silicon film and forming an insulating oxide film is performed.

摘要翻译： 本发明提供抑制在晶片上形成的单晶膜以外的硅膜表面发生异常的技术。 在步骤S1中在晶片上形成硅膜，并且在步骤S10中形成的晶片的硅表面上形成用作用于抑制表面异常的异常抑制膜的氧化膜。 通过使用诸如臭氧水或过氧化氢溶液的化学溶液，通过多晶硅的表面氧化形成异常抑制膜。 在硅表面上形成异常抑制膜之后，根据需要去除异常抑制膜，例如异常生长抑制膜，然后进行图案化硅膜并形成绝缘氧化膜的工艺。

公开(公告)号：US08595666B2

公开(公告)日：2013-11-26

申请号：US13382437

申请日：2010-05-14

申请人： Koichi Hayakawa ,  Takehiro Hirai ,  Yutaka Tandai ,  Tamao Ishikawa ,  Tsunehiro Sakai ,  Kazuhisa Hasumi ,  Kazunori Nemoto ,  Katsuhiko Ichinose ,  Yuji Takagi

发明人： Koichi Hayakawa ,  Takehiro Hirai ,  Yutaka Tandai ,  Tamao Ishikawa ,  Tsunehiro Sakai ,  Kazuhisa Hasumi ,  Kazunori Nemoto ,  Katsuhiko Ichinose ,  Yuji Takagi

IPC分类号： G06F17/50

CPC分类号： G01N21/8851 ,  G01N21/95607

摘要： A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.

摘要翻译： 通过精确地确定设计布局图案和缺陷之间的重叠状态，有效地和有效地分类缺陷。 这导致系统缺陷的简单识别。 通过半导体器件的缺陷检查或检查获得的缺陷图像与设计布局数据自动匹配。 缺陷叠加在目标层的至少一层，目标层上方的层和目标层正下方的层的设计布局图案上。 缺陷的重叠状态被确定为图案内，图案上或图案之外，并且缺陷被自动分类。

公开(公告)号：US20120131529A1

公开(公告)日：2012-05-24

申请号：US13382437

申请日：2010-05-14

申请人： Koichi Hayakawa ,  Takehiro Hirai ,  Yutaka Tandai ,  Tamao Ishikawa ,  Tsunehiro Sakai ,  Kazuhisa Hasumi ,  Kazunori Nemoto ,  Katsuhiko Ichinose ,  Yuji Takagi

发明人： Koichi Hayakawa ,  Takehiro Hirai ,  Yutaka Tandai ,  Tamao Ishikawa ,  Tsunehiro Sakai ,  Kazuhisa Hasumi ,  Kazunori Nemoto ,  Katsuhiko Ichinose ,  Yuji Takagi

IPC分类号： G06F17/50

CPC分类号： G01N21/8851 ,  G01N21/95607

摘要： A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.

摘要翻译： 通过精确地确定设计布局图案和缺陷之间的重叠状态，有效地和有效地分类缺陷。 这导致系统缺陷的简单识别。 通过半导体器件的缺陷检查或检查获得的缺陷图像与设计布局数据自动匹配。 缺陷叠加在目标层的至少一层，目标层上方的层和目标层正下方的层的设计布局图案上。 缺陷的重叠状态被确定为图案内，图案上或图案之外，并且缺陷被自动分类。