Compensation of non-volatile memory chip non-idealities by program pulse adjustment
    1.
    发明授权
    Compensation of non-volatile memory chip non-idealities by program pulse adjustment 有权
    通过程序脉冲调整来补偿非易失性存储器芯片的非理想性

    公开(公告)号:US08472255B2

    公开(公告)日:2013-06-25

    申请号:US13605714

    申请日:2012-09-06

    IPC分类号: G11C11/34

    摘要: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

    摘要翻译: 为了对一组非易失性存储元件进行编程,将一组编程脉冲施加到非易失性存储元件的控制门(或其它终端)。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中,在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中,在制造非易失性存储元件之后计算脉冲幅度。

    Temperature compensation of select gates in non-volatile memory
    2.
    发明授权
    Temperature compensation of select gates in non-volatile memory 有权
    非易失性存储器中选择门的温度补偿

    公开(公告)号:US07463528B2

    公开(公告)日:2008-12-09

    申请号:US11958534

    申请日:2007-12-18

    IPC分类号: G11C11/34 G11C16/06

    摘要: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.

    摘要翻译: 使用非选择字线的温度补偿读取电压和/或用于NAND串的漏极或源极选择栅极的选择栅极对非易失性存储元件执行读取和验证操作。 在一种方法中,当读取或验证电压被施加到所选择的字线时,温度补偿的读取电压被施加到未选择的字线并选择栅极。 直接与所选字线相邻的字线可以接收不被温度补偿的电压,或者被降低程度的温度补偿。 施加到所选字线的读取或验证电压也可以进行温度补偿。 温度补偿也可以说明字线位置。

    ADJUSTING RESISTANCE OF NON-VOLATILE MEMORY USING DUMMY MEMORY CELLS
    3.
    发明申请
    ADJUSTING RESISTANCE OF NON-VOLATILE MEMORY USING DUMMY MEMORY CELLS 有权
    使用DUMMY MEMORY CELLS调节非易失性记忆电阻

    公开(公告)号:US20080273388A1

    公开(公告)日:2008-11-06

    申请号:US11688874

    申请日:2007-03-21

    IPC分类号: G11C11/34

    摘要: In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data memory cells can be changed to account for different programmed data patterns.

    摘要翻译: 在一些非易失性存储系统中,在块的底部,块的顶部和/或其他位置处制造具有伪字线的数据存储单元块。 通过选择性地编程虚拟字线上的存储器单元,可以改变与数据存储单元相关联的电阻以考虑不同的编程数据模式。

    Soft bit data transmission for error correction control in non-volatile memory
    4.
    发明申请
    Soft bit data transmission for error correction control in non-volatile memory 有权
    软比特数据传输用于非易失性存储器中的纠错控制

    公开(公告)号:US20080244338A1

    公开(公告)日:2008-10-02

    申请号:US11694947

    申请日:2007-03-31

    IPC分类号: G11C29/00

    CPC分类号: G06F11/1068 G11C2029/0411

    摘要: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

    摘要翻译: 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中,初始可靠性度量(诸如对数似然比)被用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果解码失败,则从存储器读取软数据位。 在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。 在一个实施例中,使用软比特比较级的多个子集从存储器读取第二软比特。 当在比较级的第二子集读取时,可以基于第一子集数据执行解码。

    METHOD FOR OPERATING NON-VOLATILE MEMORY USING TEMPERATURE COMPENSATION OF VOLTAGES OF UNSELECTED WORD LINES AND SELECT GATES
    5.
    发明申请
    METHOD FOR OPERATING NON-VOLATILE MEMORY USING TEMPERATURE COMPENSATION OF VOLTAGES OF UNSELECTED WORD LINES AND SELECT GATES 有权
    使用不受限制的字线和选择门的电压的温度补偿来操作非易失性存储器的方法

    公开(公告)号:US20070291566A1

    公开(公告)日:2007-12-20

    申请号:US11424800

    申请日:2006-06-16

    摘要: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.

    摘要翻译: 使用非选择字线的温度补偿读取电压和/或用于NAND串的漏极或源极选择栅极的选择栅极对非易失性存储元件执行读取和验证操作。 在一种方法中,当读取或验证电压被施加到所选择的字线时,温度补偿的读取电压被施加到未选择的字线并选择栅极。 直接与所选字线相邻的字线可以接收不被温度补偿的电压,或者被降低程度的温度补偿。 施加到所选字线的读取或验证电压也可以进行温度补偿。 温度补偿也可以说明字线位置。

    Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
    6.
    发明授权
    Method for decoding data in non-volatile storage using reliability metrics based on multiple reads 有权
    使用基于多个读取的可靠性度量来解码非易失性存储器中的数据的方法

    公开(公告)号:US08468424B2

    公开(公告)日:2013-06-18

    申请号:US13024676

    申请日:2011-02-10

    IPC分类号: H03M13/00 G11C29/00

    摘要: Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge.

    摘要翻译: 使用迭代概率解码和多次读取操作来解码存储在非易失性存储器中的数据,以实现更高的可靠性。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中,初始可靠性度量(诸如对数似然比)被用于解码一组非易失性存储元件的读取数据。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果没有发生收敛,例如在设定的时间周期内,再次感测到非易失性存储元件的状态,则调整解码器中的可靠性度量的当前值,并且解码再次尝试收敛。

    Soft Bit Data Transmission For Error Correction Control In Non-Volatile Memory
    7.
    发明申请
    Soft Bit Data Transmission For Error Correction Control In Non-Volatile Memory 有权
    软比特数据传输用于非易失性存储器中的误差校正控制

    公开(公告)号:US20110252283A1

    公开(公告)日:2011-10-13

    申请号:US13164401

    申请日:2011-06-20

    IPC分类号: G06F11/25

    CPC分类号: G06F11/1068 G11C2029/0411

    摘要: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

    摘要翻译: 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中,初始可靠性度量(诸如对数似然比)被用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果解码失败,则从存储器读取软数据位。 在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。 在一个实施例中,使用软比特比较级的多个子集从存储器读取第二软比特。 当在比较级的第二子集读取时,可以基于第一子集数据执行解码。

    COMPENSATION OF NON-VOLATILE MEMORY CHIP NON-IDEALITIES BY PROGRAM PULSE ADJUSTMENT
    8.
    发明申请
    COMPENSATION OF NON-VOLATILE MEMORY CHIP NON-IDEALITIES BY PROGRAM PULSE ADJUSTMENT 有权
    通过程序脉冲调整补偿非易失性内存芯片非理想

    公开(公告)号:US20110235428A1

    公开(公告)日:2011-09-29

    申请号:US13151938

    申请日:2011-06-02

    IPC分类号: G11C16/10

    摘要: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

    摘要翻译: 为了对一组非易失性存储元件进行编程,将一组编程脉冲施加到非易失性存储元件的控制门(或其它终端)。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中,在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中,在制造非易失性存储元件之后计算脉冲幅度。

    MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE
    9.
    发明申请
    MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE 有权
    基于距离的多位线路电压

    公开(公告)号:US20090080265A1

    公开(公告)日:2009-03-26

    申请号:US11861571

    申请日:2007-09-26

    IPC分类号: G11C16/24 G11C7/12 G11C16/26

    摘要: An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

    摘要翻译: 非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件,连接到所选择的字线的第二组非易失性存储元件,与所选字线连接的第一组位线 第一组非易失性存储元件,与第二组非易失性存储元件通信的第二组位线,位于第一位置并连接到第一组位线的第一组感测模块, 以及位于第二位置并连接到第二组位线的第二组感测模块。 第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。 第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

    METHOD FOR DECODING DATA IN NON-VOLATILE STORAGE USING RELIABILITY METRICS BASED ON MULTIPLE READS
    10.
    发明申请
    METHOD FOR DECODING DATA IN NON-VOLATILE STORAGE USING RELIABILITY METRICS BASED ON MULTIPLE READS 有权
    基于多项阅读的可靠性量度来解密非易失存储数据的方法

    公开(公告)号:US20080250300A1

    公开(公告)日:2008-10-09

    申请号:US11693649

    申请日:2007-03-29

    IPC分类号: G11C7/10 H03M13/00

    摘要: Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.

    摘要翻译: 使用迭代概率解码和多次读取操作来解码存储在非易失性存储器中的数据,以实现更高的可靠性。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中,初始可靠性度量(诸如对数似然比)被用于解码一组非易失性存储元件的读取数据。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果没有发生收敛,例如在设定的时间周期内,再次感测到非易失性存储元件的状态,则调整解码器中的可靠性度量的当前值,并且解码再次尝试收敛。 在另一种方法中,初始可靠性度量是基于多次读取。 可以在解码发生之前准备存储基于感测状态的可靠性度量和调整的表。