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    ULTRA-SECURE ACCELERATORS
    3.
    发明申请
    ULTRA-SECURE ACCELERATORS 审中-公开

    公开(公告)号：US20190236022A1

    公开(公告)日：2019-08-01

    申请号：US16377230

    申请日：2019-04-07

    申请人： Vinodh Gopal ,  Wajdi Feghali ,  Raghunandan Makaram

    发明人： Vinodh Gopal ,  Wajdi Feghali ,  Raghunandan Makaram

    IPC分类号： G06F12/109 ,  G06F3/06

    CPC分类号： G06F12/109 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0673

    摘要： Methods and apparatus for ultra-secure accelerators. New ISA enqueue (ENQ) instructions with a wrapping key (WK) are provided to facilitate secure access to on-chip and off-chip accelerators in computer platforms and systems. The ISA ENQ with WK instructions include a dest operand having an address of an accelerator portal and a scr operand having the address of a request descriptor in system memory defining a job to be performed by an accelerator and including a wrapped key. Execution of the instruction writes a record including the src and a WK to the portal, and the record is enqueued in an accelerator queue if a slot is available. The accelerator reads the enqueued request descriptor and uses the WK to unwrap the wrapped key, which is then used to decrypt encrypted data read from one or more buffers in memory. The accelerator then performs one or more functions on the decrypted data as defined by the job and writes the output of the processing back to memory with optional encryption.

    USING AUTHENTICATED MANIFESTS TO ENABLE EXTERNAL CERTIFICATION OF MULTI-PROCESSOR PLATFORMS
    4.
    发明申请
    USING AUTHENTICATED MANIFESTS TO ENABLE EXTERNAL CERTIFICATION OF MULTI-PROCESSOR PLATFORMS 有权
    使用认证机构启用多处理器平台的外部认证

    公开(公告)号：US20150178226A1

    公开(公告)日：2015-06-25

    申请号：US14140254

    申请日：2013-12-24

    申请人： Vincent R. Scarlata ,  Simon P. Johnson ,  Vladimir Beker ,  Jesse Walker ,  Carlos V. Rozas ,  Amy L. Santoni ,  Ittai Anati ,  Raghunandan Makaram ,  Francis X. McKeen ,  Uday R. Savagaonkar

    发明人： Vincent R. Scarlata ,  Simon P. Johnson ,  Vladimir Beker ,  Jesse Walker ,  Carlos V. Rozas ,  Amy L. Santoni ,  Ittai Anati ,  Raghunandan Makaram ,  Francis X. McKeen ,  Uday R. Savagaonkar

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1466 ,  G06F21/74 ,  G06F2212/1052

    摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a plurality of processing devices communicatively coupled to the architecturally protected memory, each processing device comprising a first processing logic to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory, or preventing an unauthorized access to the architecturally protected memory; wherein each processing device further comprises a second processing logic to establish a secure communication channel with a second processing device of the processing system, employ the secure communication channel to synchronize a platform identity key representing the processing system, and transmit a platform manifest comprising the platform identity key to a certification system.

    摘要翻译： 用于将输出表面位图安全传递到显示引擎的系统和方法。 一个示例处理系统包括：架构受保护的存储器; 以及多个处理设备，通信地耦合到架构保护的存储器，每个处理设备包括第一处理逻辑，以通过执行以下至少一个来实现架构保护的执行环境：执行驻留在架构保护的存储器中的指令，或者防止未授权的 访问架构受保护的内存; 其中每个处理设备还包括第二处理逻辑，用于与所述处理系统的第二处理设备建立安全通信信道，采用所述安全通信信道来同步代表所述处理系统的平台标识密钥，并发送包括所述平台的平台清单 认证系统的身份密钥。

    SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES
    5.
    发明申请
    SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES 有权
    支持存储地址范围的可配置安全级别

    公开(公告)号：US20170024573A1

    公开(公告)日：2017-01-26

    申请号：US14803956

    申请日：2015-07-20

    申请人： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

    发明人： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

    IPC分类号： G06F21/62 ,  G06F21/60

    CPC分类号： G06F21/62 ,  G06F21/602 ,  G06F21/64 ,  G06F21/78 ,  G06F2221/2113

    摘要： A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

    摘要翻译： 公开了一种实现用于支持存储器地址范围的可配置安全级别的技术的处理器。 在一个实施例中，处理器包括处理核心，存储器控制器，可操作地耦合到处理核心，以访问片外存储器中的数据和可操作地耦合到存储器控制器的存储器加密引擎（MEE）。 所述MEE响应于检测相对于与所述片外存储器相关联的存储器地址范围内的存储器地址识别的存储器位置的存储器访问操作，基于存储的值来识别与所述存储器位置相关联的安全级别指示符 在安全范围寄存器上。 鉴于安全级别指示符，MEE进一步访问与片外存储器的存储器地址范围相关联的数据项的至少一部分。