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公开(公告)号：US11558064B2
公开(公告)日：2023-01-17
申请号：US17616643
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： Daiguo Xu , Hequan Jiang , Ruzhang Li , Jianan Wang , Guangbing Chen , Yuxin Wang , Dongbing Fu , Liang Li , Yan Wang
摘要： SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.
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公开(公告)号：US11362666B2
公开(公告)日：2022-06-14
申请号：US17264298
申请日：2018-12-13
发明人： Tao Liu , Jian'an Wang , Yuxin Wang , Guangbing Chen , Dongbing Fu , Ruzhang Li , Shengdong Hu , Zhengping Zhang , Jun Luo , Daiguo Xu , Minming Deng , Yan Wang
IPC分类号： H03K23/00 , H03K23/44 , H03K3/356 , H03K5/15 , H03K23/42 , H03K23/50 , H03K23/52 , H03K23/66
摘要： The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.
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公开(公告)号：US10291245B2
公开(公告)日：2019-05-14
申请号：US15742835
申请日：2015-08-20
发明人： Jie Pu , Gangyi Hu , Xiaofeng Shen , Xueliang Xu , Dongbing Fu , Ruitao Zhang , Youhua Wang , Yuxin Wang , Guangbing Chen , Ruzhang Li
摘要： The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.
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4.发明授权公开(公告)号：US10979066B1
公开(公告)日：2021-04-13
申请号：US16497806
申请日：2017-09-11
发明人： Zhengbo Huang , Ting Li , Yong Zhang , Ruzhang Li , Guangbing Chen , Yabo Ni
摘要： The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.
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公开(公告)号：US11595052B2
公开(公告)日：2023-02-28
申请号：US17623613
申请日：2019-07-26
发明人： Ting Li , Gangyi Hu , Ruzhang Li , Yong Zhang , Dongbing Fu , Zhengbo Huang , Yabo Ni , Jian'an Wang , Guangbing Chen
摘要： A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.
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公开(公告)号：US10425065B2
公开(公告)日：2019-09-24
申请号：US16064658
申请日：2017-01-19
发明人： Daiguo Xu , Gangyi Hu , Ruzhang Li , Jianan Wang , Guangbing Chen , Yuxin Wang , Dongbing Fu , Tao Liu , Lu Liu , Minming Deng , Hanfu Shi , Xu Wang
摘要： A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.
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