公开(公告)号：US06807124B2

公开(公告)日：2004-10-19

申请号：US10347434

申请日：2003-01-21

申请人： Nobuhiro Tsuda ,  Koji Nii ,  Shoji Okuda

发明人： Nobuhiro Tsuda ,  Koji Nii ,  Shoji Okuda

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A memory device that consumes no wasteful power in selecting memory cells and achieves high operating speed and size and cost reductions, is provided. In reading of memory cell information, only a single memory cell in a single local block is activated through a read word line. Specifically, AND circuits are provided in correspondence with all memory cells. Each AND circuit receives as its inputs a block select signal for selecting one of the local blocks and an in-block memory cell select signal for selecting one of the memory cells in each local block in a common manner among the local blocks. The outputs from the AND circuits are applied to read word lines. Unselected memory cells are not activated and therefore no current flows from those memory cells to local read bit lines, thereby preventing wasteful power consumption.

摘要翻译： 提供了在选择存储器单元中消耗浪费电力并实现高操作速度和尺寸和成本降低的存储器件。 在读取存储单元信息时，通过读字线仅激活单个本地块中的单个存储单元。 具体地，与所有存储单元相对应地提供AND电路。 每个AND电路接收用于选择本地块之一的块选择信号和块内存储单元选择信号，用于以局部块中的共同方式选择每个本地块中的一个存储单元。 来自“与”电路的输出被应用于读取字线。 未选择的存储单元不被激活，因此没有电流从这些存储器单元流到本地读取位线，从而防止浪费的功耗。

公开(公告)号：US06535417B2

公开(公告)日：2003-03-18

申请号：US09837233

申请日：2001-04-19

申请人： Nobuhiro Tsuda ,  Koji Nii

发明人： Nobuhiro Tsuda ,  Koji Nii

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.

公开(公告)号：US06292419B1

公开(公告)日：2001-09-18

申请号：US09791566

申请日：2001-02-26

申请人： Nobuhiro Tsuda

发明人： Nobuhiro Tsuda

IPC分类号： G11C700

摘要： The synchronous semiconductor memory device related to the present invention is a synchronous semiconductor memory device in which for one data read signal, the respective data corresponding to a plurality of addresses are sequentially read out from a memory cell in synchronism with an external clock signal, and which comprises a control circuit which executes control according to an externally inputted control signal so as to output only the data corresponding to one address from the memory cell for one data read signal.

公开(公告)号：US08063415B2

公开(公告)日：2011-11-22

申请号：US12178204

申请日：2008-07-23

申请人： Nobuhiro Tsuda

发明人： Nobuhiro Tsuda

IPC分类号： H01L23/52

CPC分类号： H01L27/0207

摘要： CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.

摘要翻译： CMOS反相器包含在标准单元中。 电源线电连接到CMOS反相器，并且包括下层互连和上层互连。 下层互连沿着彼此相邻并且在边界上的标准单元的边界延伸。 从平面观察，上层互连比下层互连更多地位于标准单元内。 CMOS反相器通过上层互连电连接到下层互连。 因此，获得能够实现更高速度和更高集成度的半导体器件。

公开(公告)号：US5343432A

公开(公告)日：1994-08-30

申请号：US669725

申请日：1991-03-14

申请人： Ryuichi Matsuo ,  Ryuichi Kosugi ,  Nobuhiro Tsuda ,  Osamu Ishizaki

发明人： Ryuichi Matsuo ,  Ryuichi Kosugi ,  Nobuhiro Tsuda ,  Osamu Ishizaki

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C8/18 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/12 ,  G11C8/18

摘要： A semiconductor memory device includes an array of memory cells arranged in rows and columns; a plurality of word lines connected to the rows of the memory cells; a plurality of bit lines connected to the columns of the memory cells; word line selection means; bit line selection means; and equalizing means for equalizing the bit line to a desired voltage level in response to an address signal, and for terminating the equalization in response to change in a signal on a word line according to change in the address signal.

摘要翻译： 半导体存储器件包括排列成行和列的存储单元阵列; 连接到存储器单元的行的多个字线; 连接到存储器单元的列的多个位线; 字线选择手段; 位线选择手段; 以及均衡装置，用于响应于地址信号将位线均衡到期望的电压电平，并且响应于根据地址信号的变化在字线上的信号的变化来终止均衡。

公开(公告)号：US08264011B2

公开(公告)日：2012-09-11

申请号：US13248965

申请日：2011-09-29

申请人： Nobuhiro Tsuda

发明人： Nobuhiro Tsuda

IPC分类号： H01L23/52

CPC分类号： H01L27/0207

摘要： CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.

摘要翻译： CMOS反相器包含在标准单元中。 电源线电连接到CMOS反相器，并且包括下层互连和上层互连。 下层互连沿着彼此相邻并且在边界上的标准单元的边界延伸。 从平面观察，上层互连比下层互连更多地位于标准单元内。 CMOS反相器通过上层互连电连接到下层互连。 因此，获得能够实现更高速度和更高集成度的半导体器件。

公开(公告)号：US5186789A

公开(公告)日：1993-02-16

申请号：US799993

申请日：1991-11-29

申请人： Nobuhiro Tsuda ,  Hirofumi Yamada ,  Hiroyuki Kado ,  Takao Tohda

发明人： Nobuhiro Tsuda ,  Hirofumi Yamada ,  Hiroyuki Kado ,  Takao Tohda

IPC分类号： G01B21/30 ,  B44C1/22 ,  B81C1/00 ,  C03C15/00 ,  C23F1/00 ,  G01B7/34 ,  G01Q60/38 ,  G01Q70/14 ,  H01J37/28 ,  H01L21/306

CPC分类号： G01Q60/38 ,  B82Y35/00

摘要： A cantilever stylus suited for use in an atomic force microscope is made in the following processes: forming a first film on a substrate; forming a second film of metallic material on an external surface of the first film; forming a photoresist film on an external surface of the second film by making use of a photolithography technique; performing etching with respect to the second film with only a portion thereof covered with the photoresist film left on the first film; and further performing etching with respect to the first film with the second film being used as a resist film so that the first film may be configured into a cantilever stylus.

公开(公告)号：US08710552B2

公开(公告)日：2014-04-29

申请号：US13538602

申请日：2012-06-29

申请人： Nobuhiro Tsuda ,  Hidekatsu Nishimaki ,  Hiroshi Omura ,  Yuko Yoshifuku

发明人： Nobuhiro Tsuda ,  Hidekatsu Nishimaki ,  Hiroshi Omura ,  Yuko Yoshifuku

IPC分类号： H01L27/088

CPC分类号： H01L27/0928 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11803 ,  H01L27/11898

摘要： A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.

摘要翻译： pMIS区域设置在沿第一方向延伸并且穿过多个标准单元和第一外围边缘中的每一个的边界之间。 nMIS区域设置在边界和第二周边边缘之间。 电源布线和接地布线分别沿着第一和第二外围边缘延伸。 多个pMIS布线和多个nMIS布线分别布置在沿着第一方向延伸并且沿第二方向以单个间距布置的多个第一虚拟线和多条第二虚拟线上。 最接近边界的第一虚拟线和最靠近边界的第二虚拟线之间具有大于单个间距的间距。

公开(公告)号：US08237203B2

公开(公告)日：2012-08-07

申请号：US12536319

申请日：2009-08-05

申请人： Nobuhiro Tsuda ,  Hidekatsu Nishimaki ,  Hiroshi Omura ,  Yuko Yoshifuku

发明人： Nobuhiro Tsuda ,  Hidekatsu Nishimaki ,  Hiroshi Omura ,  Yuko Yoshifuku

IPC分类号： H01L27/088

CPC分类号： H01L27/0928 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11803 ,  H01L27/11898

摘要： A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.

摘要翻译： pMIS区域设置在沿第一方向延伸并且穿过多个标准单元和第一外围边缘中的每一个的边界之间。 nMIS区域设置在边界和第二周边边缘之间。 电源布线和接地布线分别沿着第一和第二外围边缘延伸。 多个pMIS布线和多个nMIS布线分别布置在沿着第一方向延伸并且沿第二方向以单个间距布置的多个第一虚拟线和多条第二虚拟线上。 最接近边界的第一虚拟线和最靠近边界的第二虚拟线之间具有大于单个间距的间距。

公开(公告)号：US06208576B1

公开(公告)日：2001-03-27

申请号：US09231870

申请日：1999-01-14

申请人： Nobuhiro Tsuda

发明人： Nobuhiro Tsuda

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078

摘要： The synchronous semiconductor memory device related to the present invention is a synchronous semiconductor memory device in which for one data read signal, the respective data corresponding to a plurality of addresses are sequentially read out from a memory cell in synchronism with an external clock signal, and which comprises a control circuit which executes control according to an externally inputted control signal so as to output only the data corresponding to one address from the memory cell for one data read signal.

摘要翻译： 与本发明有关的同步半导体存储器件是同步半导体存储器件，其中对于一个数据读取信号，与外部时钟信号同步地从存储器单元顺序读出与多个地址相对应的各个数据，以及 其包括控制电路，该控制电路根据外部输入的控制信号执行控制，以仅从一个数据读取信号的存储器单元输出对应于一个地址的数据。