公开(公告)号：US5166553A

公开(公告)日：1992-11-24

申请号：US364461

申请日：1989-06-12

申请人： Nobuo Kotera ,  Kiichi Yamashita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Yasushi Hatta ,  Minoru Nagata

发明人： Nobuo Kotera ,  Kiichi Yamashita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Yasushi Hatta ,  Minoru Nagata

IPC分类号： G05F3/24 ,  G05F3/26 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03K17/14

CPC分类号： H03K17/145 ,  G05F3/262

摘要： A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.

摘要翻译： 公开了一种包括用于传递输出信号而不受FET的阈值电压变化影响的第一和第二FET的半导体电路。 根据半导体电路的一种实际形式，其栅极和源极彼此短路的附加FET的漏极 - 源极电流路径并联连接到栅极和漏极的第一FET的漏极 - 源极电流路径 使第二FET的电压 - 电流特性与第一和另外的FET的并联组合一致。 根据半导体电路的另一种实际形式，分压电路并联连接到第一FET的漏极 - 源极电流路径，并且来自分压电路的分压输出电压施加在每个的栅极和源极之间 第一和第二FET。

公开(公告)号：US4857769A

公开(公告)日：1989-08-15

申请号：US143385

申请日：1988-01-13

申请人： Nobuo Kotera ,  Kiichi Yamashita ,  Taizo Kinoshita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Minoru Nagata

发明人： Nobuo Kotera ,  Kiichi Yamashita ,  Taizo Kinoshita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Minoru Nagata

IPC分类号： H03K19/003

CPC分类号： H03K19/00384

摘要： This invention relates to a threshold voltage detection circuit for detecting the threshold voltage of field effect transistors (FETs) and to a semiconductor circuit capable of a stable operation irrespective of the fluctuation of the threshold voltage by utilizing this threshold voltage detection circuit. The source-drain path of first FET is connected in series with that of second FET having substantially the same threshold voltage as that of the first FET and the conductances of these first and second FETs are set to a predetermined ratio to generate a voltage drop associated with the threshold voltage in the first FET. This voltage drop can be used for detecting the threshold voltage and for level-shifting. The output of the series connection of the first and second FETs is applied to the gate of a constant current FET having the same threshold voltage as that of the first and second FETs and the drain current of the constant current FET can thus be set irrespective of the fluctuation of the threshold voltage.

摘要翻译： 本发明涉及一种阈值电压检测电路，用于通过利用该阈值电压检测电路来检测场效应晶体管（FET）的阈值电压和能够稳定工作的半导体电路，而与阈值电压的波动无关。 第一FET的源极 - 漏极路径与具有与第一FET基本相同的阈值电压的第二FET的源极 - 漏极路径串联连接，并且将这些第一和第二FET的电导设置为预定的比率以产生相关的电压降 与第一FET中的阈值电压。 该电压降可用于检测阈值电压和电平转换。 第一和第二FET的串联连接的输出被施加到具有与第一和第二FET相同的阈值电压的恒流FET的栅极，因此可以设定恒定电流FET的漏极电流，而不管 阈值电压的波动。

公开(公告)号：US4847550A

公开(公告)日：1989-07-11

申请号：US143802

申请日：1988-01-14

申请人： Satoshi Tanaka ,  Hirotoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata ,  Kiichi Yamashita ,  Tomoyuki Watanabe

发明人： Satoshi Tanaka ,  Hirotoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata ,  Kiichi Yamashita ,  Tomoyuki Watanabe

IPC分类号： G05F3/24

CPC分类号： G05F3/245 ,  G05F3/247

摘要： A constant voltage circuit according to this invention comprises first means attenuating or dividing fluctuating voltage and an amplifying FET, to the gate of which the output attenuated or divided by the first means is applied and whose drain is connected with the fluctuating voltage through load means. The attenuation ratio or division ratio of the first means, the mutual conductance of the amplifying FET and the impedance of the load means are so set that the voltage drop across the load means cancels the fluctuating amount of the fluctuating voltage. Consequently an output voltage, which is maintained substantially constant, is obtained at the drain of the amplifying FET, independently of fluctuations in the fluctuating voltage, and thus a constant voltage circuit can be obtained. A constant current circuit according to this invention utilizes the constant voltage circuit described above. The output voltage of the constant voltage circuit is supplied to the gate of the constant current FET. Consequently a current, which is maintained substantially constant, flows through the drain-source path of this constant current FET and thus a constant current circuit can be obtained.

公开(公告)号：US4881044A

公开(公告)日：1989-11-14

申请号：US139790

申请日：1987-12-30

申请人： Taizo Kinoshita ,  Satoshi Tanaka ,  Hirotoshi Tanaka ,  Nobuo Kotera ,  Minoru Nagata

发明人： Taizo Kinoshita ,  Satoshi Tanaka ,  Hirotoshi Tanaka ,  Nobuo Kotera ,  Minoru Nagata

IPC分类号： H03F3/45

CPC分类号： H03F3/45385

摘要： A wide-band and high-gain differential amplifier adapted to amplifying transmitted optical signals of the GHz band is constituted by GaAs MESFET's.Two MESFET's Q1 and Q2 are differentially connected to each other. Drains of Q1 and Q2 are connected to load resistances R.sub.L and R.sub.L via a source-drain path of other MESFET's Q3 and Q4 whose gates are grounded in AC-wise.Current by-passing means 4, 4 are connected to the sources of other MESFET's Q3, Q4. DC bias currents of the differential pair of MESFET's Q1, Q2 are set to relatively large values to increase the mutual conductance gm of the differential pair of MESFET's Q1, Q2. Despite a large DC bias current, the current by-passing means 4, 4 decrease the DC voltage drops across the load resistances R.sub.L, R.sub.L, and enable the differntial amplifier to operate on a low power source voltage.

公开(公告)号：US4825145A

公开(公告)日：1989-04-25

申请号：US133914

申请日：1987-12-16

申请人： Hirotoshi Tanaka ,  Satoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata

发明人： Hirotoshi Tanaka ,  Satoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata

IPC分类号： G05F3/24

CPC分类号： G05F3/247

摘要： A constant current circuit includes a first FET providing an input reference current flow, a second FET providing an output current flow and a non-linear impedance element connected between the drain and the gate of the first FET. By setting a parameter of the non-linear impedance element and a parameter of the first FET to have a specific relationship with each other, the output current can be maintained at a substantially definite value irrespective of relatively large variations of the input reference current.

摘要翻译： 恒流电路包括提供输入参考电流的第一FET，提供输出电流的第二FET和连接在第一FET的漏极和栅极之间的非线性阻抗元件。 通过将非线性阻抗元件的参数和第一FET的参数设置为具有特定的关系，输出电流可以保持在基本上确定的值，而与输入参考电流的相对大的变化无关。

公开(公告)号：US5132752A

公开(公告)日：1992-07-21

申请号：US658463

申请日：1991-02-22

申请人： Yasunari Umemoto ,  Nobuo Kotera ,  Kiichi Ueyanagi ,  Norikazu Hashimoto ,  Nobutoshi Matsunaga ,  Yasuo Wada ,  Shoji Shukuri ,  Noboru Masuda ,  Takehisa Hayashi ,  Hirotoshi Tanaka

发明人： Yasunari Umemoto ,  Nobuo Kotera ,  Kiichi Ueyanagi ,  Norikazu Hashimoto ,  Nobutoshi Matsunaga ,  Yasuo Wada ,  Shoji Shukuri ,  Noboru Masuda ,  Takehisa Hayashi ,  Hirotoshi Tanaka

IPC分类号： H01L29/10 ,  H01L29/812

CPC分类号： H01L29/1075 ,  H01L29/812 ,  Y10S257/903

摘要： A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.

摘要翻译： 形成在半绝缘体或化合物半导体衬底上的场效应晶体管包括形成源极区，漏极区和沟道层的第一半导体层以及具有与第一半导体层相反的导通型的第二半导体层。 第二半导体层被掺杂以使其完全耗尽。 因此，与衬底相邻的第二半导体层的一部分将保持导电。 具有这种结构的场效应晶体管防止短沟道效应和由于α-粒子引起的软误差。 还使用耦合到第二半导体层的控制电极的特征和反馈装置来提供阈值电压控制装置。

公开(公告)号：US4518868A

公开(公告)日：1985-05-21

申请号：US278730

申请日：1981-06-29

申请人： Yutaka Harada ,  Kunio Yamashita ,  Nobuo Kotera ,  Hirotoshi Tanaka

发明人： Yutaka Harada ,  Kunio Yamashita ,  Nobuo Kotera ,  Hirotoshi Tanaka

IPC分类号： H01L27/18 ,  H01L39/02 ,  H01L39/22 ,  H03K17/92 ,  H03K19/195

CPC分类号： H03K17/92 ,  H01L27/18 ,  H01L39/025 ,  Y10S505/865

摘要： A superconductive large-scale integrated circuit chip comprises a plurality of pads, a superconductive line which short-circuits respectively adjacent pairs of the pads, and an input buffer circuit. The input buffer circuit includes a Josephson junction which is either in a superconducting state or a finite voltage state in response to a magnetic field established by current that is supplied to the superconductive line by flowing in from one of the two pads and flowing out from the other pad. The input buffer circuit wave-shapes the externally supplied signal into an amplitude-controlled signal, and the latter signal is led by a superconductive line to a circuit within the chip which requires the signal. Even when the external signal current has become abnormally great due to noise, etc., any circuit situated halfway within the chip can be prevented from malfunctioning from the magnetic flux generated by the large current.

摘要翻译： 超导大规模集成电路芯片包括多个焊盘，分别相邻焊盘对短路的超导线和输入缓冲电路。 输入缓冲电路包括约瑟夫逊结，其响应于由电流建立的磁场处于超导状态或有限电压状态，该电流通过从两个焊盘中的一个流入并从其中流出而被提供给超导线 其他垫 输入缓冲器电路将外部提供的信号波形成幅度控制信号，后一个信号由超导线引导到需要信号的芯片内的电路。 即使当外部信号电流由于噪声等而变得异常大时，可以防止位于芯片中间的任何电路从由大电流产生的磁通发生故障。

公开(公告)号：US4803527A

公开(公告)日：1989-02-07

申请号：US876466

申请日：1986-06-20

申请人： Yasushi Hatta ,  Kazumichi Mitsusada ,  Hirotoshi Tanaka ,  Takehisa Hayashi

发明人： Yasushi Hatta ,  Kazumichi Mitsusada ,  Hirotoshi Tanaka ,  Takehisa Hayashi

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L21/8232 ,  H01L27/02 ,  H01L27/06 ,  H01L29/90 ,  H01L29/78

CPC分类号： H01L27/0605 ,  H01L27/0251

摘要： Disclosed is a semiconductor integrated circuit device forming MESFETs by use of a semi-insulator GaAs substrate which prevents destruction of an electrostatic destruction protect circuit and a Schottky junction of an internal circuit by causing a part of electrostatic energy, which is applied to external terminals, to flow from a semiconductor region connected to the external terminals into another semiconductor region which is formed in the vicinity of the semiconductor region described above and to which a predetermined fixed potential is applied.

摘要翻译： 公开了一种通过使用半绝缘体GaAs衬底形成MESFET的半导体集成电路器件，其通过施加施加到外部端子的一部分静电能来防止静电破坏保护电路和内部电路的肖特基结的破坏， 从连接到外部端子的半导体区域流到形成在上述半导体区域附近并且施加预定固定电位的另一个半导体区域。

公开(公告)号：US4954866A

公开(公告)日：1990-09-04

申请号：US247250

申请日：1988-09-21

申请人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

发明人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/0605 ,  H01L27/1116 ,  H01L27/105

摘要： A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.

摘要翻译： 公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层 第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。 例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下 由载流子浓度低的P型层构成。 形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。 此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加 外围电路部分保持高速运行的内存。

公开(公告)号：US4697110A

公开(公告)日：1987-09-29

申请号：US555618

申请日：1983-11-28

申请人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

发明人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0952 ,  H03K17/14 ,  H03K19/094

CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

摘要： An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.

摘要翻译： 用于半导体电路的输入缓冲器设置有源极跟随器电路，该源极跟随器电路由其栅极具有与其连接的输入端的第一FET和与第一FET的导电类型相同的第二FET组成，漏极连接到 直接或通过至少一个电平移位二极管的第一FET的源极，并且其栅电极被提供控制电压。 输入缓冲器还包括直接或通过至少一个电平移位二极管连接到第二FET的漏电极的FET反相器电路。 输入缓冲器的输出信号是从FET反相器电路得出的。 本发明的一个特别优点在于，它允许输入缓冲器响应于处于预定电压范围内的输入信号而将其输出从一个电平切换到另一个电平，而与FET中的逻辑阈值电平波动无关，并且耦合到 输入缓冲区。