公开(公告)号：US4857769A

公开(公告)日：1989-08-15

申请号：US143385

申请日：1988-01-13

申请人： Nobuo Kotera ,  Kiichi Yamashita ,  Taizo Kinoshita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Minoru Nagata

发明人： Nobuo Kotera ,  Kiichi Yamashita ,  Taizo Kinoshita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Minoru Nagata

IPC分类号： H03K19/003

CPC分类号： H03K19/00384

摘要： This invention relates to a threshold voltage detection circuit for detecting the threshold voltage of field effect transistors (FETs) and to a semiconductor circuit capable of a stable operation irrespective of the fluctuation of the threshold voltage by utilizing this threshold voltage detection circuit. The source-drain path of first FET is connected in series with that of second FET having substantially the same threshold voltage as that of the first FET and the conductances of these first and second FETs are set to a predetermined ratio to generate a voltage drop associated with the threshold voltage in the first FET. This voltage drop can be used for detecting the threshold voltage and for level-shifting. The output of the series connection of the first and second FETs is applied to the gate of a constant current FET having the same threshold voltage as that of the first and second FETs and the drain current of the constant current FET can thus be set irrespective of the fluctuation of the threshold voltage.

摘要翻译： 本发明涉及一种阈值电压检测电路，用于通过利用该阈值电压检测电路来检测场效应晶体管（FET）的阈值电压和能够稳定工作的半导体电路，而与阈值电压的波动无关。 第一FET的源极 - 漏极路径与具有与第一FET基本相同的阈值电压的第二FET的源极 - 漏极路径串联连接，并且将这些第一和第二FET的电导设置为预定的比率以产生相关的电压降 与第一FET中的阈值电压。 该电压降可用于检测阈值电压和电平转换。 第一和第二FET的串联连接的输出被施加到具有与第一和第二FET相同的阈值电压的恒流FET的栅极，因此可以设定恒定电流FET的漏极电流，而不管 阈值电压的波动。

公开(公告)号：US4847550A

公开(公告)日：1989-07-11

申请号：US143802

申请日：1988-01-14

申请人： Satoshi Tanaka ,  Hirotoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata ,  Kiichi Yamashita ,  Tomoyuki Watanabe

发明人： Satoshi Tanaka ,  Hirotoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata ,  Kiichi Yamashita ,  Tomoyuki Watanabe

IPC分类号： G05F3/24

CPC分类号： G05F3/245 ,  G05F3/247

摘要： A constant voltage circuit according to this invention comprises first means attenuating or dividing fluctuating voltage and an amplifying FET, to the gate of which the output attenuated or divided by the first means is applied and whose drain is connected with the fluctuating voltage through load means. The attenuation ratio or division ratio of the first means, the mutual conductance of the amplifying FET and the impedance of the load means are so set that the voltage drop across the load means cancels the fluctuating amount of the fluctuating voltage. Consequently an output voltage, which is maintained substantially constant, is obtained at the drain of the amplifying FET, independently of fluctuations in the fluctuating voltage, and thus a constant voltage circuit can be obtained. A constant current circuit according to this invention utilizes the constant voltage circuit described above. The output voltage of the constant voltage circuit is supplied to the gate of the constant current FET. Consequently a current, which is maintained substantially constant, flows through the drain-source path of this constant current FET and thus a constant current circuit can be obtained.

公开(公告)号：US4825145A

公开(公告)日：1989-04-25

申请号：US133914

申请日：1987-12-16

申请人： Hirotoshi Tanaka ,  Satoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata

发明人： Hirotoshi Tanaka ,  Satoshi Tanaka ,  Taizo Kinoshita ,  Nobuo Kotera ,  Minoru Nagata

IPC分类号： G05F3/24

CPC分类号： G05F3/247

摘要： A constant current circuit includes a first FET providing an input reference current flow, a second FET providing an output current flow and a non-linear impedance element connected between the drain and the gate of the first FET. By setting a parameter of the non-linear impedance element and a parameter of the first FET to have a specific relationship with each other, the output current can be maintained at a substantially definite value irrespective of relatively large variations of the input reference current.

摘要翻译： 恒流电路包括提供输入参考电流的第一FET，提供输出电流的第二FET和连接在第一FET的漏极和栅极之间的非线性阻抗元件。 通过将非线性阻抗元件的参数和第一FET的参数设置为具有特定的关系，输出电流可以保持在基本上确定的值，而与输入参考电流的相对大的变化无关。

公开(公告)号：US4881044A

公开(公告)日：1989-11-14

申请号：US139790

申请日：1987-12-30

申请人： Taizo Kinoshita ,  Satoshi Tanaka ,  Hirotoshi Tanaka ,  Nobuo Kotera ,  Minoru Nagata

发明人： Taizo Kinoshita ,  Satoshi Tanaka ,  Hirotoshi Tanaka ,  Nobuo Kotera ,  Minoru Nagata

IPC分类号： H03F3/45

CPC分类号： H03F3/45385

摘要： A wide-band and high-gain differential amplifier adapted to amplifying transmitted optical signals of the GHz band is constituted by GaAs MESFET's.Two MESFET's Q1 and Q2 are differentially connected to each other. Drains of Q1 and Q2 are connected to load resistances R.sub.L and R.sub.L via a source-drain path of other MESFET's Q3 and Q4 whose gates are grounded in AC-wise.Current by-passing means 4, 4 are connected to the sources of other MESFET's Q3, Q4. DC bias currents of the differential pair of MESFET's Q1, Q2 are set to relatively large values to increase the mutual conductance gm of the differential pair of MESFET's Q1, Q2. Despite a large DC bias current, the current by-passing means 4, 4 decrease the DC voltage drops across the load resistances R.sub.L, R.sub.L, and enable the differntial amplifier to operate on a low power source voltage.

公开(公告)号：US5166553A

公开(公告)日：1992-11-24

申请号：US364461

申请日：1989-06-12

申请人： Nobuo Kotera ,  Kiichi Yamashita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Yasushi Hatta ,  Minoru Nagata

发明人： Nobuo Kotera ,  Kiichi Yamashita ,  Hirotoshi Tanaka ,  Satoshi Tanaka ,  Yasushi Hatta ,  Minoru Nagata

IPC分类号： G05F3/24 ,  G05F3/26 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03K17/14

CPC分类号： H03K17/145 ,  G05F3/262

摘要： A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.

摘要翻译： 公开了一种包括用于传递输出信号而不受FET的阈值电压变化影响的第一和第二FET的半导体电路。 根据半导体电路的一种实际形式，其栅极和源极彼此短路的附加FET的漏极 - 源极电流路径并联连接到栅极和漏极的第一FET的漏极 - 源极电流路径 使第二FET的电压 - 电流特性与第一和另外的FET的并联组合一致。 根据半导体电路的另一种实际形式，分压电路并联连接到第一FET的漏极 - 源极电流路径，并且来自分压电路的分压输出电压施加在每个的栅极和源极之间 第一和第二FET。

公开(公告)号：US20100176869A1

公开(公告)日：2010-07-15

申请号：US12686613

申请日：2010-01-13

申请人： Koji Horie ,  Minoru Nagata

发明人： Koji Horie ,  Minoru Nagata

IPC分类号： H01L37/00

CPC分类号： H03F1/302 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/447 ,  H03F2200/451

摘要： A temperature compensation circuit according to an embodiment of the present invention includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region in which a temperature is lower than a predetermined temperature, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region in which the temperature is equal to or greater than the predetermined temperature, and a transistor having a control terminal supplied with the bias current. The bias circuit includes a first current generating circuit configured to generate a first current increasing in proportion to the absolute temperature, a second current generating circuit configured to generate a second current that does not flow in the low-temperature region and flows in the high-temperature region, and a control circuit configured to control the second current and having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current, and is configured to generate a third current by adding the first current to the second current, and output the bias current depending on or equal to the third current.

摘要翻译： 根据本发明实施例的温度补偿电路包括：偏置电路，被配置为输出与温度低于预定温度的低温区域中的绝对温度成比例地增加的电流值的偏置电流， 并且具有比在温度等于或大于预定温度的高温区域中与绝对温度成比例的电流值的电流值更大的电流值，以及具有提供偏置电流的控制端子的晶体管。 偏置电路包括：第一电流产生电路，被配置为产生与绝对温度成比例的第一电流;第二电流产生电路，被配置为产生不在低温区域中流动并在高温区域中流动的第二电流; 温度区域和控制电路，被配置为控制第二电流并具有能够与外部电阻器连接的连接端子，用于调整第二电流的大小，并且被配置为通过将第一电流加到第一电流中来产生第三电流 并且根据或等于第三电流输出偏置电流。

公开(公告)号：US5842123A

公开(公告)日：1998-11-24

申请号：US425736

申请日：1995-04-20

申请人： Nobuo Hamamoto ,  Tadashi Onishi ,  Tatsundo Suzuki ,  Minoru Nagata ,  Kenichi Mizuishi ,  Yosuke Tyojamori

发明人： Nobuo Hamamoto ,  Tadashi Onishi ,  Tatsundo Suzuki ,  Minoru Nagata ,  Kenichi Mizuishi ,  Yosuke Tyojamori

IPC分类号： G08B3/10 ,  G08B5/22 ,  H04M3/533 ,  H04M11/02 ,  H04W88/18 ,  H04M11/10

CPC分类号： H04W88/187 ,  G08B3/1025 ,  G08B5/229 ,  H04M11/022 ,  H04M3/533 ,  H04M2203/609

摘要： A radio paging system with voice transfer function for transmitting a voice message input from an ordinary push-button telephone set to a small-sized receive-only unsophisticated radio pager. A paging station is provided to transmit by radio the message from a telephone network to the radio pager as follows: voice information constituting the message is first converted from analog to digital format, compressed, stored in memory, and scrambled by a privacy function part for transmission. The radio pager in turn demodulates the received information, stores it in memory, retrieves a necessary message therefrom as designated, descrambles the designated message from scrambled state, expands the message from compressed state, and outputs the message as an audible output. In this manner, the user carrying the radio pager is able to get the message from the caller without the risk of being tapped by a third party.

公开(公告)号：US4860086A

公开(公告)日：1989-08-22

申请号：US26254

申请日：1987-03-16

申请人： Tohru Nakamura ,  Masahiko Ogirima ,  Kazuo Nakazato ,  Takao Miyazaki ,  Naoki Yamamoto ,  Minoru Nagata ,  Shojiro Sugaki, deceased

发明人： Tohru Nakamura ,  Masahiko Ogirima ,  Kazuo Nakazato ,  Takao Miyazaki ,  Naoki Yamamoto ,  Minoru Nagata ,  Shojiro Sugaki, deceased

IPC分类号： H01L23/485 ,  H01L23/532

CPC分类号： H01L23/53271 ,  H01L23/485 ,  H01L2924/0002

摘要： A semiconductor device is constructed so that an insulation film is provided in regions other than a protruding portion of a substrate. A polycrystalline silicon layer and a metal silicide layer are formed over said insulation film to provide a multi-layer structure, and a take-out portion for at least one of the emitter, base, and collector members of a bipolar transistor provided in the mesa region is constituted by a film of this multi-layer structure. By virtue of the use of metal silicide together with the polycrystalline silicon, a very low resistance is achieved which enhances the device's operating speed. Further, the metal silicide is separated from the protruding portion of the substrate by a portion of the polycrystalline silicon to provide a smooth interface with the substrate. This smooth interface significantly reduces crystal defects in the single crystal substrate.

摘要翻译： 构造半导体器件，使得绝缘膜设置在除了衬底的突出部分之外的区域中。 在所述绝缘膜上形成多晶硅层和金属硅化物层以提供多层结构，以及设置在台面中的双极晶体管的发射极，基极和集电极构件中的至少一个的取出部分 区域由该多层结构的膜构成。 由于金属硅化物与多晶硅一起使用，所以实现了非常低的电阻，这增强了器件的工作速度。 此外，金属硅化物通过多晶硅的一部分与衬底的突出部分分离，以提供与衬底的平滑界面。 这种平滑的界面显着地减少了单晶衬底中的晶体缺陷。

公开(公告)号：US4825281A

公开(公告)日：1989-04-25

申请号：US435552

申请日：1982-10-21

申请人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

发明人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

IPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/331 ,  H01L27/06 ,  H01L29/423 ,  H01L29/70 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L23/48 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L29/42304 ,  H01L29/72 ,  H01L29/732 ,  H01L29/735

摘要： A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

摘要翻译： 一种半导体器件，其中晶体管的有源区形成在设置在绝缘膜中的开口中，电极由形成在绝缘膜上的多晶硅膜引出，发射极和基极的上表面和暴露表面 的绝缘膜基本上均匀。

公开(公告)号：US08456227B2

公开(公告)日：2013-06-04

申请号：US13046953

申请日：2011-03-14

申请人： Kenichi Hirashiki ,  Norio Hagiwara ,  Tsutomu Nakashima ,  Minoru Nagata

发明人： Kenichi Hirashiki ,  Norio Hagiwara ,  Tsutomu Nakashima ,  Minoru Nagata

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.

摘要翻译： 在一个实施例中，电流镜电路包括第一至第四绝缘栅场效应晶体管（FET）和偏置电路。 第一和第二FET的栅电极彼此连接。 第三FET的源电极连接到第一FET的漏电极，第三FET的漏电极连接到第一和第二FET的栅电极以及电流输入端。 第四FET的栅电极与第三FET的栅电极连接，第四FET的源电极与第二FET的漏极连接，第四FET的漏极成为电流输出端。 偏置电路被配置为向第三和第四FET的栅电极提供偏置电压。