公开(公告)号：USD660992S1

公开(公告)日：2012-05-29

申请号：US29401492

申请日：2011-09-12

申请人： Nobuyuki Mase ,  Masashi Sakata ,  Yasuyuki Saito ,  Masato Matsumoto

设计人： Nobuyuki Mase ,  Masashi Sakata ,  Yasuyuki Saito ,  Masato Matsumoto

公开(公告)号：US09413201B2

公开(公告)日：2016-08-09

申请号：US13810838

申请日：2011-07-20

申请人： Yasuyuki Saito ,  Noriaki Hino ,  Tomoaki Kaimori ,  Kenichi Nakayama ,  Yoshimi Mori ,  Keiji Oda

发明人： Yasuyuki Saito ,  Noriaki Hino ,  Tomoaki Kaimori ,  Kenichi Nakayama ,  Yoshimi Mori ,  Keiji Oda

IPC分类号： H02K3/28 ,  H02K21/14

摘要： A rotating electrical machine includes: a stator core; a stator winding; and a rotor. Cross conductors connect slot conductors to run astride slots with the slot pitch N+1 at coil ends on one side and run astride slots with the slot pitch N−1 at coil ends on another side, with N representing a number of slots per pole; the stator winding includes slot conductor groups each having a plurality of slot conductors; the plurality of slot conductors in each slot conductor group are inserted at a predetermined number Ns of successive slots so that the slot conductors in the slot conductor group take successive slot positions and successive layer positions; and the number Ns is set so that Ns=NSPP+NL when NSPP represents a number of slots per phase per pole and a number of layers is expressed as 2×NL.

公开(公告)号：US08847454B2

公开(公告)日：2014-09-30

申请号：US13504283

申请日：2010-08-24

申请人： Yasuyuki Saito ,  Noriaki Hino ,  Tomoaki Kaimori ,  Shinji Sugimoto

发明人： Yasuyuki Saito ,  Noriaki Hino ,  Tomoaki Kaimori ,  Shinji Sugimoto

IPC分类号： H02K1/27

CPC分类号： H02K1/276 ,  B60L7/14 ,  B60L7/18 ,  B60L11/123 ,  B60L11/14 ,  B60L15/007 ,  B60L15/2009 ,  B60L2210/40 ,  B60L2240/421 ,  B60L2240/423 ,  Y02T10/6217 ,  Y02T10/641 ,  Y02T10/645 ,  Y02T10/7077 ,  Y02T10/7241 ,  Y02T10/7275

摘要： A rotating electric machine includes a stator and a rotor. Each of magnetic poles of the rotor includes a magnet insertion hole, a permanent magnet that is inserted in the magnet insertion hole, and a nonmagnetic portion formed between the permanent magnet and an auxiliary salient pole. A portion of the rotor core located toward the stator relative to the nonmagnetic portion function as a bridge portion connecting a magnetic pole peace with the auxiliary salient pole. A side of the nonmagnetic portion located toward the stator includes a first side at the bridge portion, extending along a virtual circular arc passing through the permanent magnet insertion hole closest to the stator, and a side of the nonmagnetic portion located toward the auxiliary salient pole includes a second side extending away from the stator, with the first side and the second side connected through a curved line.

摘要翻译： 旋转电机包括定子和转子。 转子的每个磁极包括磁体插入孔，插入到磁体插入孔中的永磁体以及形成在永磁体和辅助凸极之间的非磁性部分。 相对于非磁性部分朝向定子的转子芯的一部分起到连接磁极和平与辅助凸极的桥接部分的作用。 位于定子的非磁性部分的一侧包括在桥接部分处的第一侧，沿着穿过最靠近定子的永磁体插入孔的虚拟圆弧延伸，并且朝向辅助凸极位于非磁性部分的一侧 包括远离定子延伸的第二侧，第一侧和第二侧通过曲线连接。

公开(公告)号：US20140049134A1

公开(公告)日：2014-02-20

申请号：US14114297

申请日：2012-05-01

申请人： Hidetoshi Koka ,  Satoshi Kikuchi ,  Yutaka Matsunobu ,  Noriaki Hino ,  Keiji Oda ,  Yasuyuki Saito ,  Manabu Oshida ,  Kazuo Nishihama

发明人： Hidetoshi Koka ,  Satoshi Kikuchi ,  Yutaka Matsunobu ,  Noriaki Hino ,  Keiji Oda ,  Yasuyuki Saito ,  Manabu Oshida ,  Kazuo Nishihama

IPC分类号： H02K17/16

CPC分类号： H02K17/165 ,  H02K17/205

摘要： Induction electrical rotating machine includes a stator which has plural stator slots 114 formed at a predetermined spacing in a circumferential direction of a stator iron core 111 and in which a stator winding 120 is accommodated in the plural stator slots 114, and a rotor 130 in which a rotor bar 132 extending in an axial direction of the rotor iron core 111 is provided in a plural number at a spacing in a circumferential direction and in which a pair of end rings that shorts the plural rotor bars 132 at ends in the axial direction is provided. A shape of a stator-side end, of a sectional shape within a plane orthogonal to a rotor axial direction of the rotor bar 132, is asymmetrical and a notch 133 is formed.

摘要翻译： 感应旋转电机包括定子，该定子具有多个定子槽114，该定子槽114沿定子铁芯111的圆周方向以预定的间隔形成，定子绕组120容纳在多个定子槽114中，转子130中 在转子铁芯111的轴向上延伸的转子条132沿圆周方向间隔设置多个，并且在轴向的端部使多个转子杆132短路的一对端环为 提供。 在与转子杆132的转子轴向正交的平面内的截面形状的定子侧端部的形状是不对称的，并且形成有切口133。

公开(公告)号：US20080309383A1

公开(公告)日：2008-12-18

申请号：US12107069

申请日：2008-04-21

申请人： Naoki Yada ,  Yasuyuki Saito ,  Yasushi Shibatsuka ,  Katsunori Koike ,  Mitsuhiko Okutsu

发明人： Naoki Yada ,  Yasuyuki Saito ,  Yasushi Shibatsuka ,  Katsunori Koike ,  Mitsuhiko Okutsu

IPC分类号： H03L7/00

CPC分类号： H03L7/08 ,  G06F1/08 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/2481 ,  H03K2005/00039 ,  H03K2005/00143 ,  H03L7/085

摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.

摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。

公开(公告)号：US07385869B2

公开(公告)日：2008-06-10

申请号：US11797579

申请日：2007-05-04

申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

IPC分类号： G11C7/00

CPC分类号： G11C16/12 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30

摘要： A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.

摘要翻译： 从外部提供第一电压的数据处理装置包括CPU，第一电压产生电路，第二电压产生电路，时钟发生电路和可被CPU访问的非易失性存储器。 第一电压产生电路产生其电压电平低于第一电压的第二电压。 时钟发生电路从第一电压产生电路提供第二电压并产生时钟信号，并且第二电压产生电路从第一电压产生电路提供第二电压和来自时钟发生电路的时钟信号，并产生 其电压电平高于第一电压的第二电压，用于提供给非易失性存储器。

公开(公告)号：US07382681B2

公开(公告)日：2008-06-03

申请号：US11708346

申请日：2007-02-21

申请人： Naoki Yada ,  Yasuyuki Saito ,  Yasushi Shibatsuka ,  Katsunori Koike ,  Mitsuhiko Okutsu

发明人： Naoki Yada ,  Yasuyuki Saito ,  Yasushi Shibatsuka ,  Katsunori Koike ,  Mitsuhiko Okutsu

IPC分类号： G11C8/00

CPC分类号： H03L7/08 ,  G06F1/08 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/2481 ,  H03K2005/00039 ,  H03K2005/00143 ,  H03L7/085

摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.

摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。

公开(公告)号：US07236419B2

公开(公告)日：2007-06-26

申请号：US11365499

申请日：2006-03-02

申请人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

发明人： Eiichi Ishikawa ,  Yasuyuki Saito ,  Masanao Sato ,  Naoki Yada ,  Kiyoshi Matsubara

IPC分类号： G11C7/00

CPC分类号： G11C16/12 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30

摘要： A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.

摘要翻译： 提供一种半导体处理装置，其包括非易失性存储单元，电压产生单元和第一端子。 电压产生单元产生由从半导体处理装置的外部提供的操作电压产生的第一电压，并将第一电压提供给用于在其中存储数据的非易失性存储单元。 第一端子将由电压产生单元产生的第一电压提供给半导体处理装置的外部。 通过第一端子提供到半导体处理装置外部的第一电压允许检查第一电压的电压电平并校正该电压电平。

公开(公告)号：US20060227650A1

公开(公告)日：2006-10-12

申请号：US11446217

申请日：2006-06-05

申请人： Naoki Yada ,  Yasuyuki Saito ,  Yasushi Shibatsuka ,  Katsunori Koike ,  Mitsuhiko Okutsu

发明人： Naoki Yada ,  Yasuyuki Saito ,  Yasushi Shibatsuka ,  Katsunori Koike ,  Mitsuhiko Okutsu

IPC分类号： G11C8/00

CPC分类号： H03L7/08 ,  G06F1/08 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/2481 ,  H03K2005/00039 ,  H03K2005/00143 ,  H03L7/085

摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.

公开(公告)号：US07075469B2

公开(公告)日：2006-07-11

申请号：US11246170

申请日：2005-10-11

申请人： Naoki Yada ,  Yasuyuki Saito

发明人： Naoki Yada ,  Yasuyuki Saito

IPC分类号： H03M1/78

CPC分类号： H03M1/1023 ,  H03M1/46 ,  H03M1/682 ,  H03M1/765

摘要： A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.

摘要翻译： 一种包括能够将通过外部端子接收的模拟信号转换为数字信号的A / D转换器的半导体集成电路。 A / D转换器包括：用于产生参考电压的梯形电阻器; 一组第一运算放大器，每个接收梯形电阻器的输出电压; 一组第一开关，每个能够使第一运算放大器的相应一个输入端子和输出端子短路，从而允许相应的第一运算放大器的偏移校正; 以及用于将每个第一运算放大器的输出电压与模拟信号进行比较的比较器电路。 A / D转换器可以减少梯形电阻器的电流输出，并加快采样电容器的充电和放电。