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公开(公告)号：US5274677A
公开(公告)日：1993-12-28
申请号：US752124
申请日：1991-08-29
CPC分类号： G06F1/10
摘要： A clock distribution system includes a clock generation and distribution part for generating a clock signal and distributing the generated clock signal to a plurality of destinations, slots in each of which a clock reception unit can be detachably mounted, and a plurality of transmission lines coupling the clock generation and distribution part to the slots. Each slot includes a circuit for generating a mount state signal which indicates whether or not the slot is mounted with a clock reception unit, and for supplying the mount state signal to the clock generation and distribution part via a transmission line. This mount state signal has a first state when no clock receiving unit is mounted in the slot and has a second state when a clock receiving unit is mounted in the slot. The clock generation and distribution part includes a circuit for receiving the mount state signal from each slot and for transmitting via the transmission line the clock signal to each slot from which a mount state signal having the second state is received.
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公开(公告)号：US5812559A
公开(公告)日：1998-09-22
申请号：US949705
申请日：1992-09-23
申请人： Hiroshi Nakaide , Fumihiko Saito , Shinzi Hiyama , Koji Ikuta
发明人： Hiroshi Nakaide , Fumihiko Saito , Shinzi Hiyama , Koji Ikuta
摘要： A control method and apparatus for the examination of multiport RAM(s) connected between a CPU on a CPU side and a hardware circuit on a hardware circuit side. The method and apparatus are for use in a device comprising a single RAM or more. For instance, the device may have a first RAM and a second RAM having ports on CPU and a hardware circuit side of the RAMs. Each one port on the CPU side is connected to a CPU. The method and apparatus examine the ports on the hardware circuit as well as the CPU side ports. The method may comprise steps of reading data stored in the first RAM from a port on the hardware circuit of the first RAM and writing the data in the second RAM from the port on the hardware circuit side of the second RAM using a RAM examination controller. The data read from the one port of the first RAM on the CPU side of the RAMs is compared with the data from the other port of the second RAM on the CPU side of the RAMs. The operation of ports of the first RAM and the second RAM on the hardware circuit side of the RAMs is examined.
摘要翻译： 一种用于检查连接在CPU侧的CPU与硬件电路侧的硬件电路之间的多端口RAM的控制方法和装置。 该方法和装置用于包括单个RAM或更多的设备。 例如，该设备可以具有第一RAM和第二RAM，其具有CPU上的端口和RAM的硬件电路侧。 CPU侧的每个端口都连接到CPU。 该方法和装置检查硬件电路以及CPU侧端口上的端口。 该方法可以包括从第一RAM的硬件电路上的端口读取存储在第一RAM中的数据的步骤，并使用RAM检查控制器从第二RAM的硬件电路侧的端口写入第二RAM中的数据。 从RAM的CPU侧的第一RAM的一个端口读取的数据与来自RAM的CPU侧的第二RAM的另一个端口的数据进行比较。 检查RAM的硬件电路侧的第一RAM和第二RAM的端口的操作。
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3.发明授权Mounting information-collecting device, connector, and mounting information-collecting method 失效安装信息收集装置，连接器和安装信息收集方法公开(公告)号：US06707543B2
公开(公告)日：2004-03-16
申请号：US09989865
申请日：2001-11-19
IPC分类号： G01J142
CPC分类号： G02B6/4246 , G02B6/29362 , G02B6/29368 , G02B6/29389 , G02B6/29395 , G02B6/3817 , G02B6/3821 , G02B6/3895 , G02B6/3897 , G02B6/43 , H05K1/0266 , H05K1/14 , H05K13/08
摘要： There are disclosed a mounting information-collecting device which is capable of collecting mounting information concerning mounted statuses of circuit boards with high accuracy and efficiency, as well as a connector and a mounting information-collecting method therefor. A light-emitting device emits an optical signal. A plurality of optical signal-processing elements each apply processing to the optical signal in a manner unique to a corresponding one of the circuit boards to thereby generate a processed optical signal. A mounting information-collecting device receives the processed optical signal and detects whether or not the processing has been applied, to thereby collect the mounting information.
摘要翻译： 公开了一种安装信息收集装置，其能够以高精度和高效率收集关于电路板的安装状态的安装信息，以及连接器及其安装信息收集方法。 发光装置发出光信号。 多个光信号处理元件以对应的一个电路板独有的方式对光信号进行处理，从而生成经处理的光信号。 安装信息收集装置接收经处理的光信号并检测是否应用了处理，从而收集安装信息。
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公开(公告)号：US5420855A
公开(公告)日：1995-05-30
申请号：US185753
申请日：1994-01-21
申请人： Akio Morimoto , Hiroshi Nakaide
发明人： Akio Morimoto , Hiroshi Nakaide
CPC分类号： H04Q11/08
摘要： A multi-port time switch element for cross-connecting an n-channel multiplexed data includes m input ports for receiving m n-channel multiplexed data, a memory part for alternately writing and reading the n-channel multiplexed data, m selectors for writing and reading the n-channel multiplexed data so that each of the m selectors receives m.times.n data read from the memory part and selects one of the m.times.n data n times in an arbitrary sequence to output an n-channel multiplexed data, and m output ports for outputting the m n-channel multiplexed data read from the m selectors.
摘要翻译： 用于交叉连接n信道复用数据的多端口时间切换元件包括用于接收m n信道复用数据的m个输入端口，用于交替写入和读取n信道复用数据的存储器部分，用于写入的m个选择器和 读取n信道多路复用数据，使得m个选择器中的每一个接收从存储器部分读取的m×n数据，并以任意顺序选择m×n个数据n次，以输出n信道复用数据，并输出m个输出端口 从m个选择器读取的m个信道复用数据。
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5.发明授权Mounting information-collecting device, connector, and mounting information-collecting method 失效安装信息收集装置，连接器和安装信息收集方法公开(公告)号：US06926452B2
公开(公告)日：2005-08-09
申请号：US10746776
申请日：2003-12-23
CPC分类号： G02B6/4246 , G02B6/29362 , G02B6/29368 , G02B6/29389 , G02B6/29395 , G02B6/3817 , G02B6/3821 , G02B6/3895 , G02B6/3897 , G02B6/43 , H05K1/0266 , H05K1/14 , H05K13/08
摘要： There are disclosed a mounting information-collecting device which is capable of collecting mounting information concerning mounted statuses of circuit boards with high accuracy and efficiency, as well as a connector and a mounting information-collecting method therefor. A light-emitting device emits an optical signal. A plurality of optical signal-processing elements each apply processing to the optical signal in a manner unique to a corresponding one of the circuit boards to thereby generate a processed optical signal. A mounting information-collecting device receives the processed optical signal and detects whether or not the processing has been applied, to thereby collect the mounting information.
摘要翻译： 公开了一种安装信息收集装置，其能够以高精度和高效率收集关于电路板的安装状态的安装信息，以及连接器及其安装信息收集方法。 发光装置发出光信号。 多个光信号处理元件以对应的一个电路板独有的方式对光信号进行处理，从而生成经处理的光信号。 安装信息收集装置接收经处理的光信号并检测是否应用了处理，从而收集安装信息。
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6.发明授权
公开(公告)号：US5430723A
公开(公告)日：1995-07-04
申请号：US61218
申请日：1993-05-13
CPC分类号： H04Q11/08
摘要： A time switch control system having a cross-connect function is used for digital time-division. Multiplex communications permit desired channel settings and reduce power consumption. Identifying circuits identify which time-slot signals are to be retained by an input signal retaining memory, and output identification information to the retention memory, and to a retention memory controller. The retention memory controller stores therein the identification information from the identifying circuits, then reads out the identification information, and controls the input signal retaining memory in accordance with the contents of the identification information. Only the specified time-slot signals are stored and retained by the input signal retaining memory, thereby reducing power requirements. Exchange/output circuits exchange the time-slot signals stored in the input signal retaining memory in accordance with channel setting information, and output the exchanged signals.
摘要翻译： 具有交叉连接功能的时间切换控制系统被用于数字时分。 多路复用通信允许所需的通道设置并降低功耗。 识别电路识别由输入信号保持存储器保留哪些时隙信号，并将识别信息输出到保持存储器以及保持存储器控制器。 保持存储器控制器从识别电路存储识别信息，然后读出识别信息，并根据识别信息的内容控制输入信号保持存储器。 只有指定的时隙信号由输入信号保持存储器存储和保留，从而减少功率要求。 交换/输出电路根据信道设置信息交换存储在输入信号保持存储器中的时隙信号，并输出所交换的信号。
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公开(公告)号：US5426654A
公开(公告)日：1995-06-20
申请号：US985624
申请日：1992-12-03
CPC分类号： H03M13/091 , H03M13/6502
摘要： At a CRC transmission side of a cross connect equipment, a CRC operation is applied to received channel data of each channel independently and sequentially in every sub frame having the same number of channels, series of which sub frames set up a main frame. The resultant CRC code of each channel obtained in a preceding sub frame is coupled to the received channel data of the corresponding channel to apply the same CRC operation to the thus received channel data, thereby the accumulated result of each channel is added in the last sub frame. At a CRC reception side, a cyclic CRC operation similar to that achieved at the CRC transmission side is applied to an outgoing channel data provided with the resultant CRC codes for each channel to obtain CRC results. During the cyclic CRC operation, a CRC error that once occurs is held during the main frame.
摘要翻译： 在交叉连接设备的CRC发送侧，在具有相同数量的信道的子帧中独立且顺序地对每个信道的接收信道数据应用CRC操作，其中一系列子帧建立主帧。 在前一子帧中获得的每个信道的结果CRC码被耦合到相应信道的接收信道数据，以将相同的CRC操作应用于如此接收的信道数据，从而将每个信道的累加结果添加到最后一个子 帧。 在CRC接收侧，将与在CRC发送侧实现的循环CRC操作类似的循环CRC操作应用于每个通道提供有合成CRC码的输出信道数据，以获得CRC结果。 在循环CRC操作期间，在主帧期间保持一旦发生的CRC错误。
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8.发明授权
公开(公告)号：US4849995A
公开(公告)日：1989-07-18
申请号：US889375
申请日：1986-07-25
申请人： Hiroshi Takeo , Masanori Kajiwara , Michinobu Ohhata , Takao Moriya , Satoshi Takeda , Hiroshi Nakaide , Hiroshi Yamasaki , Toshinari Kunieda , Ikuo Washiyama
发明人： Hiroshi Takeo , Masanori Kajiwara , Michinobu Ohhata , Takao Moriya , Satoshi Takeda , Hiroshi Nakaide , Hiroshi Yamasaki , Toshinari Kunieda , Ikuo Washiyama
CPC分类号： H04J3/0608 , H04L7/048
摘要： A digital signal transmission system includes a synchronization pattern detection circuit for detecting a synchronization pattern in response to a received transmitted digital signal, a pseudo synchronization detection circuit for detecting a pseudo synchronization pattern in the form of cyclic redundancy code in response to a received transmitted digital signal, and a synchronization protection circuit for counting the synchronization pattern detection signals produced when synchronization patterns are detected in response to a synchronization pattern detection signal from the synchronization pattern detection circuit. The synchronization protection circuit includes a main synchronization counter circuit and an auxiliary synchronization counter circuit. The count of protection steps for the confirmation of synchronization recovery of the auxiliary synchronization counter circuit in accordance with synchronization or asynchronization of the main synchronization counter circuit is variable.
摘要翻译： 数字信号传输系统包括：响应于所接收的发送的数字信号来检测同步模式的同步模式检测电路;伪同步检测电路，用于响应于所接收的发送的数字信号，以循环冗余码的形式检测伪同步模式 信号和同步保护电路，用于对来自同步模式检测电路的同步模式检测信号进行检测同步模式时产生的同步模式检测信号进行计数。 同步保护电路包括主同步计数器电路和辅助同步计数器电路。 根据主同步计数器电路的同步或异步确认辅助同步计数器电路的同步恢复的保护步骤的计数是可变的。
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