公开(公告)号：US4514766A

公开(公告)日：1985-04-30

申请号：US482791

申请日：1983-04-07

申请人： Norio Koike ,  Iwao Takemoto ,  Shinya Ohba ,  Toshiaki Masuhara ,  Masaharu Kubo

发明人： Norio Koike ,  Iwao Takemoto ,  Shinya Ohba ,  Toshiaki Masuhara ,  Masaharu Kubo

IPC分类号： H04N5/345 ,  H04N5/372 ,  H04N5/3728 ,  H04N3/15

CPC分类号： H04N3/1575 ,  H01L27/14856 ,  H04N3/1537

摘要： A solid-state imaging device is provided which employs CCDs as vertical shift registers and a horizontal shift register for vertically and horizontally scanning and reading out a large number of photoelectric elements arrayed in a two-dimensional plane. The imaging device is characterized in that the photoelectric elements of each column arranged between the vertical shift registers are alternately connected to the right and left vertical shift registers. This results in the resolution of the device being enhanced sharply.

摘要翻译： 提供了一种使用CCD作为垂直移位寄存器的固态成像装置和用于垂直和水平扫描并读出排列在二维平面中的大量光电元件的水平移位寄存器。 成像装置的特征在于，布置在垂直移位寄存器之间的每列的光电元件交替地连接到左右垂直移位寄存器。 这导致设备的分辨率急剧增加。

公开(公告)号：US4559550A

公开(公告)日：1985-12-17

申请号：US548576

申请日：1983-11-04

申请人： Norio Koike ,  Shinya Ohba ,  Toshiaki Masuhara

发明人： Norio Koike ,  Shinya Ohba ,  Toshiaki Masuhara

IPC分类号： H01L21/339 ,  H01L27/148 ,  H01L29/762 ,  H04N5/335 ,  H04N5/341 ,  H04N5/357 ,  H04N5/3728 ,  H01L29/78 ,  G11C19/28 ,  H01L27/14 ,  H01L31/00

CPC分类号： H04N3/1575 ,  H01L27/14831 ,  H01L27/14868

摘要： A solid-state imager includes vertical CCD shift registers for transferring photogenerated signal charge packets produced by a group of photodiodes belonging to a first series, vertical CCD shift registers for transferring photogenerated signal charge packets produced by photodiodes belonging to a second series, a horizontal CCD shift register for receiving signal charge packets shifted through both the vertical shift registers and transferring them to an output circuit and a coupling circuit provided between the horizontal CCD shift register and both the vertical CCD shift registers, all the components being formed on a single semiconductor substrate. Through the coupling circuit, one of two series of photogenerated signal packets transferred from both the vertical CCD shift registers located adjacent to each other are transferred to the horizontal CCD shift register beneath a set of storage electrodes thereof, which is followed by the transfer of the other series of signal charge packets to the horizontal shift register beneath other set of storage electrode. The horizontal CCD shift register transfers sequentially and alternately two series of the photogenerated signal charge packets to an output circuit. Two series of the signal charge packets can thus be transferred through the single horizontal CCD shift register.

摘要翻译： 固态成像器包括垂直CCD移位寄存器，用于传送由属于第一系列的一组光电二极管产生的光生信号电荷包，用于传送由属于第二系列的光电二极管产生的光生信号电荷包的垂直CCD移位寄存器，水平CCD 移位寄存器，用于接收通过两个垂直移位寄存器移位的信号电荷数据包，并将它们传送到输出电路;以及耦合电路，设置在水平CCD移位寄存器和两个垂直CCD移位寄存器之间，所有元件都形成在单个半导体衬底上 。 通过耦合电路，从彼此相邻的垂直CCD移位寄存器传输的两个系列的光生成信号包中的一个被传送到其一组存储电极下方的水平CCD移位寄存器，其后是传送 其他系列的信号电荷包到水平移位寄存器下面的其他组存储电极。 水平CCD移位寄存器将两个系列的光生信号电荷分组顺序地和交替地传送到输出电路。 因此可以通过单个水平CCD移位寄存器传送两个系列的信号电荷包。

公开(公告)号：US4672586A

公开(公告)日：1987-06-09

申请号：US617919

申请日：1984-06-06

申请人： Katsuhiro Shimohigashi ,  Masaharu Kubo ,  Katsuki Miyauchi ,  Toshiaki Masuhara ,  Osamu Minato

发明人： Katsuhiro Shimohigashi ,  Masaharu Kubo ,  Katsuki Miyauchi ,  Toshiaki Masuhara ,  Osamu Minato

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C5/141

摘要： A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.

公开(公告)号：US4280065A

公开(公告)日：1981-07-21

申请号：US969269

申请日：1978-12-14

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

IPC分类号： H03K19/0175 ,  H03K5/02 ,  H03K19/082 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K3/01 ,  H03K19/08

CPC分类号： H03K19/09429 ,  H03K19/0823 ,  H03K19/09448 ,  H03K5/023

摘要： This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output inverter circuit which employs a bipolar transistor as a load thereof and a MOS-FET as a driver thereof, a first logical circuit which is coupled to an input terminal of the bipolar transistor, which first logical circuit is made up of a C-MOS circuit receiving an external select signal and a C-MOS circuit having an input signal transmitted thereto and whose output can be specified by the external select signal, and a second logical circuit which is coupled to an input terminal of the MOS-FET, which second logical circuit is made up of a C-MOS circuit receiving the external select signal and a C-MOS circuit having the input signal transmitted thereto. The state of the external select signal will determine whether the driver circuit output will be "float" (regardless of the input to the driver circuit) or "on" or "off" (in correspondence with the input to the driver circuit).

摘要翻译： 本发明涉及一种三态型驱动电路，其中即使输出端子伴随着大的负载，也可以高速度地产生“浮动”，“接通”或“断开”的三个可能的输出信号中的任何一个 。 三态型驱动器电路包括采用双极晶体管作为其负载的输出反相器电路和作为其驱动器的MOS-FET，耦合到双极晶体管的输入端的第一逻辑电路，第一逻辑 电路由接收外部选择信号的C-MOS电路和具有传输的输入信号的C-MOS电路组成，其输出可由外部选择信号指定，第二逻辑电路耦合到输入端 MOS-FET的端子，该第二逻辑电路由接收外部选择信号的C-MOS电路和传输了该输入信号的C-MOS电路组成。 外部选择信号的状态将决定驱动器电路输出是否为“浮动”（不管驱动电路的输入）还是“开”或“关”（与驱动电路的输入相对应）。

公开(公告)号：US4261004A

公开(公告)日：1981-04-07

申请号：US929959

申请日：1978-08-01

申请人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

发明人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

IPC分类号： H03F1/52 ,  H01L21/02 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/78 ,  H03F1/42

CPC分类号： H01L28/20 ,  H01L27/0251 ,  H01L27/0288

摘要： On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..

摘要翻译： 在形成有要形成有待保护的MOS型半导体器件的半导体衬底的表面上的绝缘膜的表面上形成有具有输入和输出端子的电阻率低于1KΩ的第一多晶硅元件， 并且具有电阻率低于1KΩ/□并且保持在固定电位的第二多晶硅部件。 该第二多晶硅部件面对第一硅部件的至少一部分，其中多晶硅的电阻率高于100KΩ，并插入其间。 第一多晶硅部件的输入端子连接到要被保护的MOS型半导体器件的输入焊盘，并且第一多晶硅部件的输出端子连接到待保护的半导体器件的输入栅极。 半导体器件的输入栅极通过利用电阻率高于100KΩ/□的多晶硅的内部的穿透效应来保护。

公开(公告)号：US4199778A

公开(公告)日：1980-04-22

申请号：US843366

申请日：1977-10-19

申请人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

发明人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

IPC分类号： H01L21/763 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/04 ,  H01L23/48 ,  H01L29/44

CPC分类号： H01L21/32155 ,  H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002

摘要： In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.

摘要翻译： 在具有多晶硅互连和金属互连的半导体集成电路中，在未掺杂的多晶硅层的预定部分中形成在多晶硅互连中含有高浓度的杂质的低电阻层，其沉积在第一绝缘膜上 半导体衬底，第二绝缘膜沉积在多晶硅层上，在未被掺杂的部分至少留在待形成的通孔周围的状态下，并且其至少部分的金属互连在与 多晶硅互连设置在第二绝缘膜上，金属互连和多晶硅互连之间的必要接触通过设置在第二绝缘膜中的通孔形成，与两个互连的相交部分相对应。

公开(公告)号：US4015281A

公开(公告)日：1977-03-29

申请号：US121375

申请日：1971-03-05

申请人： Minoru Nagata ,  Toshiaki Masuhara ,  Masaharu Kubo ,  Norikazu Hashimoto

发明人： Minoru Nagata ,  Toshiaki Masuhara ,  Masaharu Kubo ,  Norikazu Hashimoto

IPC分类号： H01L21/765 ,  H01L27/088 ,  H01L29/51 ,  H01L27/02

CPC分类号： H01L29/511 ,  H01L21/765 ,  H01L27/0883

摘要： An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.

摘要翻译： 增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上，并且通过多个层彼此电隔离，所述多个层包括例如第一SiO 2层，第二层 能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层，并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。

公开(公告)号：US4935901A

公开(公告)日：1990-06-19

申请号：US158259

申请日：1988-02-19

申请人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

发明人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

IPC分类号： G11C11/419

CPC分类号： G11C11/419

摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

公开(公告)号：US4710648A

公开(公告)日：1987-12-01

申请号：US731014

申请日：1985-05-06

申请人： Shoji Hanamura ,  Masaaki Aoki ,  Toshiaki Masuhara

发明人： Shoji Hanamura ,  Masaaki Aoki ,  Toshiaki Masuhara

IPC分类号： G11C8/18 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H03K5/1534 ,  H03K19/00 ,  H03K17/16 ,  H03K19/20

CPC分类号： H03K5/1534 ,  G11C8/18 ,  H01L27/092 ,  H01L27/10805 ,  H03K19/0016 ,  H01L27/105

摘要： Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized.

摘要翻译： 响应于信号处理开始信号，电荷被提供给处于信号处理器内的电荷存储状态的电路节点。 处理器在低温范围内操作，例如在温度低于200K的范围内。 通过这种结构，泄漏电流减小，可以获得与动态电路相当的高度积分，并且可以实现不需要任何复杂的内部/外部定时信号的静态电路的简单性。

公开(公告)号：US4581628A

公开(公告)日：1986-04-08

申请号：US424370

申请日：1982-09-27

申请人： Tateoki Miyauchi ,  Mikio Hongo ,  Masao Mitani ,  Isao Tanabe ,  Toshiaki Masuhara

发明人： Tateoki Miyauchi ,  Mikio Hongo ,  Masao Mitani ,  Isao Tanabe ,  Toshiaki Masuhara

IPC分类号： H01L21/3205 ,  H01L21/00 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/552 ,  H01L27/10 ,  H01L23/48 ,  H01L29/04

CPC分类号： H01L21/82 ,  H01L23/525 ,  H01L23/5254 ,  H01L23/552 ,  H01L2924/0002

摘要： The present invention consists in a semiconductor integrated circuit device characterized in that a circuit programming wiring layer is formed on an insulating film which is provided on a semiconductor substrate, and that a light shielding protective mask material is deposited around the circuit programming wiring layer except a program part thereof, through an insulating film.

摘要翻译： 本发明是一种半导体集成电路器件，其特征在于，在设置在半导体衬底上的绝缘膜上形成电路编程布线层，并且在电路编程布线层周围沉积遮光保护掩模材料，除了 程序部分，通过绝缘膜。