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    Fabrication process of a stack type semiconductor capacitive element
    3.
    发明授权
    Fabrication process of a stack type semiconductor capacitive element 失效
    堆叠型半导体电容元件的制造工艺

    公开(公告)号：US5858852A

    公开(公告)日：1999-01-12

    申请号：US853744

    申请日：1997-05-09

    申请人： Fumiki Aiso ,  Toshiyuki Hirota

    发明人： Fumiki Aiso ,  Toshiyuki Hirota

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L28/84

    摘要： At first, a silicon oxide layer is selectively formed on the surface of a semiconductor substrate. Next, a first amorphous silicon film doped with phosphorous in the concentration of about 1.times.10.sup.20 (atoms/cm.sup.3) and a non-doped second amorphous silicon film are deposited in sequential order. By this, an amorphous silicon layer for lower electrode constituted of the first and second amorphous silicon films is formed. Then, an HSG (unevenness) is formed on the surface of the amorphous silicon layer for lower electrode. Subsequently, the amorphous silicon layer for lower electrode is patterned to form a lower electrode of the stack type capacitive element. Thereafter, a capacitance insulation layer is formed on the upper surface and the side surface of the lower electrode. Then, over the entire surface, an upper electrode is deposited.

    摘要翻译： 首先，在半导体衬底的表面上选择性地形成氧化硅层。 接下来，依次沉积掺杂浓度为约1×10 20（原子/ cm 3）的磷和非掺杂的第二非晶硅膜的第一非晶硅膜。 由此，形成由第一和第二非晶硅膜构成的用于下电极的非晶硅层。 然后，在用于下电极的非晶硅层的表面上形成HSG（凹凸）。 随后，将用于下电极的非晶硅层图案化以形成堆叠型电容元件的下电极。 此后，在下电极的上表面和侧表面上形成电容绝缘层。 然后，在整个表面上沉积上电极。

    Method for manufacturing a semiconductor device
    4.
    发明申请
    Method for manufacturing a semiconductor device 审中-公开
    半导体器件的制造方法

    公开(公告)号：US20070042574A1

    公开(公告)日：2007-02-22

    申请号：US11503968

    申请日：2006-08-15

    申请人： Norishiro Komatsu ,  Toshiyuki Hirota

    发明人： Norishiro Komatsu ,  Toshiyuki Hirota

    IPC分类号： H01L21/00

    CPC分类号： H01L27/10852 ,  H01L28/84

    摘要： A method for manufacturing a semiconductor device that can prevent short-circuiting between gate electrodes and increases in the leakage current of a capacitive insulating film caused by the bottom electrode of the capacitor is provided. The method for manufacturing a semiconductor device according to the present invention comprises a first step for forming an amorphous silicon film on a semiconductor substrate; a second step for forming a stopper film on a surface of the amorphous silicon film to prevent migration of the surface of the amorphous silicon film; and a third step for removing the stopper film from the surface of the amorphous silicon film.

    摘要翻译： 提供了一种可以防止栅电极之间的短路并且由电容器的底部电极引起的电容绝缘膜的漏电流增加的半导体器件的制造方法。 根据本发明的制造半导体器件的方法包括：在半导体衬底上形成非晶硅膜的第一步骤; 用于在非晶硅膜的表面上形成阻挡膜以防止非晶硅膜的表面迁移的第二步骤; 以及从非晶硅膜的表面除去阻挡膜的第三步骤。

    Method for producing capacitor elements, and capacitor element
    6.
    发明授权
    Method for producing capacitor elements, and capacitor element 失效
    电容器元件的制造方法以及电容元件

    公开(公告)号：US06376328B1

    公开(公告)日：2002-04-23

    申请号：US09584947

    申请日：2000-06-01

    申请人： Fumiki Aiso ,  Toshiyuki Hirota

    发明人： Fumiki Aiso ,  Toshiyuki Hirota

    IPC分类号： H01L2120

    CPC分类号： H01L28/84 ,  H01L28/91

    摘要： A silicon layer containing microcrystal is formed on a semiconductor substrate 10 having an amorphous silicon layer 61a formed on the surface thereof (t1 and t2). Continuously, HSGs (hemispherical grains) are formed, in the same furnace, on the silicon layer 61a using microcrystal on the silicon layer 61a as a nucleus (t2 and t3). Further, a source gas containing impurities is introduced into the furnace to diffuse impurities into the HSGs (t3 and t4), wherein a lower electrode is formed. Also, during the processes from t1 through t4, the partial pressure of water and oxygen in the furnace is set to 1×10−6 Torr or less. Furthermore, during the processes from t1 through t4, the temperature in the furnace is set to 550 through 600° C.

    摘要翻译： 在具有形成在其表面上的非晶硅层61a（t1和t2）的半导体衬底10上形成含有微晶体的硅层。 连续地，在相同的炉子中，在作为核的硅层61a上使用微晶的硅层61a（t2和t3）上形成HSG（半球状晶粒）。 此外，将含有杂质的源气体引入炉中以将杂质扩散到HSG（t3和t4）中，其中形成下电极。 此外，在从t1到t4的过程中，炉中的水和氧的分压设定为1×10 -6 Torr或更小。 此外，在t1〜t4的处理中，将炉内的温度设定为550〜600℃

    Process for forming a capacitor incorporated in a semiconductor device
    7.
    发明授权
    Process for forming a capacitor incorporated in a semiconductor device 失效
    用于形成结合在半导体器件中的电容器的工艺

    公开(公告)号：US6146966A

    公开(公告)日：2000-11-14

    申请号：US859210

    申请日：1997-05-20

    申请人： Toshiyuki Hirota ,  Hirohito Watanabe ,  Fumiki Aiso ,  Shuji Fujiwara ,  Masanobu Zenke

    发明人： Toshiyuki Hirota ,  Hirohito Watanabe ,  Fumiki Aiso ,  Shuji Fujiwara ,  Masanobu Zenke

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L28/84 ,  H01L27/10852

    摘要： In a process of forming hemi-spherical silicon grains on an amorphous silicon film in accordance with the "crystal nucleation" process, in order to form crystal nuclei on a top surface and a side surface of the amorphous silicon film, SiH.sub.4 is irradiated onto the top and side surfaces of the amorphous silicon film at a stabilized temperature which is lower than, by at least 5.degree. C., an annealing temperature for growing the hemi-spherical silicon grains from the crystal nuclei, with the result that it is possible to suppress or retard the growth of the crystals growing into the amorphous silicon film from a boundary between the amorphous silicon film and an interlayer insulator film. Thereafter, the amorphous silicon film having the crystal nuclei thus formed on the surface thereof is annealed at the annealing temperature so that the hemi-spherical silicon grains are formed on the whole surface of the top and side surfaces of the amorphous silicon film.

    摘要翻译： 在根据“晶体成核”法在非晶硅膜上形成半球形硅晶粒的过程中，为了在非晶硅膜的顶表面和侧表面上形成晶核，将SiH 4照射到 该非晶硅膜的顶表面和侧表面在稳定的温度下低于至少5℃的用于从晶核生长半球形硅晶粒的退火温度，结果是可以 从非晶硅膜和层间绝缘膜之间的边界抑制或延缓从非晶硅膜生长的晶体的生长。 此后，在其表面上形成具有晶核的非晶硅膜在退火温度下退火，使得半球形硅晶粒形成在非晶硅膜的顶表面和侧表面的整个表面上。

    Capacitor incorporated in semiconductor device having a lower electrode composed of multi-layers or of graded impurity concentration
    8.
    发明授权
    Capacitor incorporated in semiconductor device having a lower electrode composed of multi-layers or of graded impurity concentration 失效
    掺入半导体器件中的电容器具有由多层或渐变杂质浓度组成的下电极

    公开(公告)号：US5959326A

    公开(公告)日：1999-09-28

    申请号：US852530

    申请日：1997-05-07

    申请人： Fumiki Aiso ,  Hirohito Watanabe ,  Toshiyuki Hirota ,  Masanobu Zenke ,  Shuji Fujiwara

    发明人： Fumiki Aiso ,  Hirohito Watanabe ,  Toshiyuki Hirota ,  Masanobu Zenke ,  Shuji Fujiwara

    IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/205 ,  H01L21/283 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01G4/06

    CPC分类号： H01L28/84

    摘要： In a capacitor incorporated in a semiconductor device, a capacitor lower plate is formed of a first amorphous silicon film on an interlayer insulator film and a second amorphous silicon film stacked on the first amorphous silicon film. A crystallization preventing film is formed between the first and second amorphous silicon films, or alternatively, the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. A stacked structure formed of the first and second amorphous silicon films is patterned into a capacitor lower plate having a top surface and a side surface, and hemispherical grains are formed on not only the top surface but also the side surface of the patterned stacked structure. In this process, crystalline growth from the interlayer insulator film is prevented by the crystallization preventing film or by the fact that the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. Thus, concaves and convexes in the form of hemispherical grains are uniformly formed on not only the top surface but also the side surface of the patterned stacked structure, so that a remarkably increased capacitance can be obtained.

    摘要翻译： 在并入半导体装置的电容器中，电容器下板由层叠绝缘膜上的第一非晶硅膜和层叠在第一非晶硅膜上的第二非晶硅膜形成。 在第一和第二非晶硅膜之间形成结晶防止膜，或者，形成第一非晶硅膜的杂质浓度低于第二非晶硅膜的杂质浓度。 由第一和第二非晶硅膜形成的堆叠结构被图案化成具有顶表面和侧表面的电容器底板，并且半球形晶粒不仅形成在图案化堆叠结构的顶表面而且形成在侧表面上。 在该方法中，通过防止结晶化膜或者形成第一非晶硅膜的杂质浓度低于第二非晶硅膜的杂质浓度来防止来自层间绝缘膜的晶体生长。 因此，半球状晶粒形式的凹凸不仅在图案化叠层结构的顶表面，而且均匀地形成，从而可以获得显着增加的电容。

    Semiconductor device manufacturing method having high aspect ratio insulating film
    9.
    再颁专利
    Semiconductor device manufacturing method having high aspect ratio insulating film 失效
    具有高纵横比绝缘膜的半导体器件制造方法

    公开(公告)号：USRE45361E1

    公开(公告)日：2015-02-03

    申请号：US14068785

    申请日：2013-10-31

    申请人： Toshiyuki Hirota

    发明人： Toshiyuki Hirota

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3081 ,  H01L21/3083 ,  H01L21/76224

    摘要： The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming the hole in a semiconductor substrate, and a stopper during removing the insulating film filled in the hole.

    摘要翻译： 本发明的目的是将绝缘膜嵌入具有高纵横比和小宽度的孔中而不发生空隙。 通过在形成半导体衬底中的孔期间分别用作掩模的分隔层和在填充在孔中的绝缘膜去除期间的止动件来减少抛光阻挡层的厚度。