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公开(公告)号：US06768691B2
公开(公告)日：2004-07-27
申请号：US10241908
申请日：2002-09-12
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066
摘要： A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.
摘要翻译： 一种半导体集成电路，包括：第一输出驱动部，其与参考时钟信号同步地输出数据信号; 第二输出驱动部，其输出规定所述数据信号的定时的数据选通信号; 以及分别控制所述第一和第二输出驱动部的驱动能力的驱动控制部。
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2.发明授权Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same 失效具有多个存储体的同步半导体存储器件及其控制方法公开(公告)号：US06885606B2
公开(公告)日：2005-04-26
申请号：US10353271
申请日：2003-01-28
IPC分类号： G01R31/30 , G01R31/28 , G01R31/3185 , G11C7/10 , G11C8/12 , G11C11/401 , G11C29/06 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C8/12
摘要： A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a command, detects whether the command is a read command or a write command, and, when detecting a read command or a write command, outputs a first control signal that enables a read operation or a write operation in the plurality of memory banks, bank select circuits which activate a second control signal to activate each of the memory banks, and bank timer circuits which deactivate the activated second control signal and perform control in such a manner that the timing with which the second control signal is deactivated in a test mode differs from that in a normal mode.
摘要翻译： 同步半导体存储器件包括从存储器单元读取数据并将数据写入存储单元的多个存储器组，接收命令的命令解码器电路，检测该命令是读命令还是写命令，以及何时 检测读取命令或写入命令，输出启用多个存储体中的读取操作或写入操作的第一控制信号，激活第二控制信号的存储体选择电路以激活每个存储体，以及存储体定时器 电路，其使激活的第二控制信号去激活并执行控制，使得在测试模式中第二控制信号被去激活的定时与正常模式不同。
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3.发明申请公开(公告)号：US20070176654A1
公开(公告)日：2007-08-02
申请号：US11668159
申请日：2007-01-29
申请人： Noriyasu Kumazaki , Keiji Maruyama
发明人： Noriyasu Kumazaki , Keiji Maruyama
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , H03K17/145 , H03K17/302
摘要： A semiconductor memory device comprises a n-channel type MOSFET in which a drain and a gate are connected to an external power supply and a source and a back gate are connected each other, a node connected to the source and the back gate of the n-channel type MOSFET, and a detector for detecting an input of the external power supply based on a potential of the node
摘要翻译： 半导体存储器件包括n沟道型MOSFET，其中漏极和栅极连接到外部电源，源极和后栅极彼此连接，连接到源极和n的栅极的节点 通道型MOSFET，以及用于基于节点的电位检测外部电源的输入的检测器
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4.发明授权公开(公告)号：US07573306B2
公开(公告)日：2009-08-11
申请号：US11668159
申请日：2007-01-29
申请人： Noriyasu Kumazaki , Keiji Maruyama
发明人： Noriyasu Kumazaki , Keiji Maruyama
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , H03K17/145 , H03K17/302
摘要： A semiconductor memory device includes a n-channel type MOSFET in which a drain and a gate are connected to an external power supply and a source and a back gate are connected each other. A node is connected to the source and the back gate of the n-channel type MOSFET, and a detector for detecting an input of the external power supply based on a potential of the node.
摘要翻译： 半导体存储器件包括其中漏极和栅极连接到外部电源并且源极和后栅极彼此连接的n沟道型MOSFET。 节点连接到n沟道型MOSFET的源极和背栅极，以及用于基于节点的电位检测外部电源的输入的检测器。
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5.发明授权Semiconductor memory device using a bandgap reference circuit and a reference voltage generator for operating under a low power supply voltage 有权使用带隙参考电路的半导体存储器件和用于在低电源电压下工作的参考电压发生器公开(公告)号：US07920439B2
公开(公告)日：2011-04-05
申请号：US11860779
申请日：2007-09-25
申请人： Noriyasu Kumazaki
发明人： Noriyasu Kumazaki
摘要： A semiconductor memory device includes a boosting power supply circuit that boosts a first voltage to a second voltage, which is higher than an external power supply. A first bandgap reference (BGR) circuit operates on the second voltage generated by the boosting power supply circuit. Thereby, the power supply circuit generates a voltage by using a bandgap reference circuit.
摘要翻译： 半导体存储器件包括将第一电压升压到高于外部电源的第二电压的升压电源电路。 第一带隙基准（BGR）电路对由升压电源电路产生的第二电压进行操作。 因此，电源电路通过使用带隙基准电路来产生电压。
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公开(公告)号：US20080239837A1
公开(公告)日：2008-10-02
申请号：US11860779
申请日：2007-09-25
申请人： Noriyasu Kumazaki
发明人： Noriyasu Kumazaki
IPC分类号： G11C5/14
摘要： A semiconductor memory device includes a boosting circuit which boosts in a second voltage higher than an external power supply by using a first voltage as a reference voltage, and a bandgap reference circuit which operates by using the second voltage generated by the boosting circuit as a power supply voltage.
摘要翻译： 半导体存储器件包括升压电路，其通过使用第一电压作为参考电压来升高比外部电源高的第二电压;以及带隙基准电路，其通过使用由升压电路产生的第二电压作为功率进行工作 电源电压。
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公开(公告)号：US08310878B2
公开(公告)日：2012-11-13
申请号：US12956423
申请日：2010-11-30
申请人： Noriyasu Kumazaki
发明人： Noriyasu Kumazaki
IPC分类号： G11C11/34
摘要： A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor. The switch circuit conducts changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal.
摘要翻译： 升压电路包括第一至第四整流元件，第一至第四MOS晶体管，第一至第四电容器和开关电路。 开关电路具有连接到第三整流元件的第一端和第四整流元件的第一端之间的第一连接节点的低电平端子，以及连接到第二整流元件的第二端之间的第二连接节点的高电平端子 第三MOS晶体管和第四MOS晶体管的第二端。 开关电路在低电平端子的电压和高电平端子之间的电压之间进行切换，以将合成的电压输出到输出端子。
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公开(公告)号：US20110249506A1
公开(公告)日：2011-10-13
申请号：US13053839
申请日：2011-03-22
申请人： Akira Umezawa , Noriyasu Kumazaki , Daisuke Arizono , Mami Kakoi
发明人： Akira Umezawa , Noriyasu Kumazaki , Daisuke Arizono , Mami Kakoi
IPC分类号： G11C16/04
摘要： A semiconductor storage device according to an embodiment includes a plurality of memory cells which electrically rewrite data by controlling the amount of charges accumulated in a floating gate formed on a well through a tunnel insulating film. The semiconductor storage device includes a well control circuit which outputs an erasure voltage to be applied to the well through an output terminal. The semiconductor storage device includes a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal. The semiconductor storage device includes a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit. The semiconductor storage device includes a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit. The semiconductor storage device includes an erase pulse control circuit which sets target voltages of the first pump circuit and the second pump circuit, on the basis of setting values to set a target voltage of the erasure voltage.
摘要翻译： 根据实施例的半导体存储装置包括多个存储单元，其通过控制通过隧道绝缘膜在阱上形成的浮动栅中积累的电荷量来电重写数据。 半导体存储装置包括井控电路，其通过输出端子输出要施加到井的擦除电压。 半导体存储装置包括：第一泵电路，其通过将输入电压升压到输出端子来输出设定的电压。 半导体存储装置包括：第二泵电路，其通过将输入电压升压到输出端子并输出高于第一泵电路的输出电压的电压来输出设定的电压。 半导体存储装置包括泵开关检测电路，其输出辅助信号以对第一泵电路和第二泵电路中的至少一个进行升压操作。 半导体存储装置包括：擦除脉冲控制电路，其基于设定值设定第一泵电路和第二泵电路的目标电压，设定擦除电压的目标电压。
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公开(公告)号：US08432744B2
公开(公告)日：2013-04-30
申请号：US13053839
申请日：2011-03-22
申请人： Akira Umezawa , Noriyasu Kumazaki , Daisuke Arizono , Mami Kakoi
发明人： Akira Umezawa , Noriyasu Kumazaki , Daisuke Arizono , Mami Kakoi
摘要： A semiconductor storage device according to an embodiment includes multiple memory cells which electrically rewrite data, a well control circuit which outputs an erasure voltage to be applied to a well through an output terminal, a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal, a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit, a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit and an erase pulse control circuit which sets target voltages of the first pump circuit and the second pump circuit, on the basis of setting values to set a target voltage of the erasure voltage.
摘要翻译： 根据实施例的半导体存储装置包括电重写数据的多个存储单元，输出通过输出端施加到阱的擦除电压的阱控制电路，第一泵电路，其通过升压输入端输出设定的电压 输出端子的电压;第二泵电路，其通过将输入电压升压到输出端子而输出电压，并输出高于第一泵电路的输出电压的电压;泵切换检测电路，其将辅助信号输出到 在第一泵电路和第二泵电路中的至少一个上执行升压操作，以及擦除脉冲控制电路，其基于设定值设定第一泵电路和第二泵电路的目标电压，以设定目标电压 的擦除电压。
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10.发明授权Nonvolatile semiconductor memory with charge storage layers and control gates 有权具有电荷存储层和控制栅极的非易失性半导体存储器公开(公告)号：US08238154B2
公开(公告)日：2012-08-07
申请号：US12552563
申请日：2009-09-02
IPC分类号： G11C16/04
CPC分类号： G11C5/147 , G11C16/0483 , G11C16/30
摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.
摘要翻译： 非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。 存储单元阵列包括存储单元。 每个位线与相应的一个存储单元的电流路径的一端电连接。 第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高 第一电压。 第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。
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