公开(公告)号：US20070010032A1

公开(公告)日：2007-01-11

申请号：US11519614

申请日：2006-09-12

申请人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

发明人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

IPC分类号： H01L21/00

CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L21/76892

摘要： A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

摘要翻译： 通过在制造过程中对缺陷的在线修复来提高半导体产量的方法包括：在模具上形成所选择的层之后检查晶片上的管芯，识别每个管芯中的缺陷，将所识别的缺陷分类为杀伤或非关键的， 对于每个杀手缺陷，确定纠正缺陷的动作，修复缺陷并将晶片返回到下一个处理步骤。 还公开了一种通过将模具分成网格并利用网格分析来找到最小侵入性修复来确定有效修复过程的方法。

公开(公告)号：US20050255611A1

公开(公告)日：2005-11-17

申请号：US10911142

申请日：2004-08-04

申请人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

发明人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L21/76892

摘要： A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

摘要翻译： 通过在制造过程中对缺陷的在线修复来提高半导体产量的方法包括：在模具上形成所选择的层之后检查晶片上的管芯，识别每个管芯中的缺陷，将所识别的缺陷分类为杀伤或非关键的， 对于每个杀手缺陷，确定纠正缺陷的动作，修复缺陷并将晶片返回到下一个处理步骤。 还公开了一种通过将模具分成网格并利用网格分析来找到最小侵入性修复来确定有效修复过程的方法。

公开(公告)号：US20060063282A1

公开(公告)日：2006-03-23

申请号：US10947069

申请日：2004-09-22

申请人： Bradley Albers ,  Thomas Esry ,  Daniel Kerr ,  Edward Martin ,  Oliver Patterson

发明人： Bradley Albers ,  Thomas Esry ,  Daniel Kerr ,  Edward Martin ,  Oliver Patterson

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  G01R31/2648 ,  G01R31/2884 ,  G01R31/307

摘要： A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

摘要翻译： 用于识别NPN双极晶体管的发射极 - 基极结中的晶体缺陷的方法和装置使用具有可以使用无源电压对比度检查的NP结的测试结构。 测试结构消除了晶体管的集电极，仅模拟发射极和基极。 如果发射极 - 基极结有缺陷，则消除集电极会消除晶片的集电极和衬底之间的NP结，从而允许电荷从衬底流到发射极，因为在测试结构中只有一个NP结存在。 在一个实施例中，测试结构位于晶片上的管芯之间，并且可以形成为几千个。

公开(公告)号：US20050068052A1

公开(公告)日：2005-03-31

申请号：US10675581

申请日：2003-09-30

申请人： Oliver Patterson ,  Michael Twiford

发明人： Oliver Patterson ,  Michael Twiford

IPC分类号： G01Q30/20 ,  G01Q60/40 ,  G01R31/307 ,  G01R31/305

CPC分类号： G01R31/307

摘要： Voltage contrast-based apparatuses, methods and systems for detection of continuity are described for use in evaluation of conducting components of a microcircuit such as a silicon wafer-based semiconductor chip. Two beams are directed to two separate conducting, electrically floating components on the sample, and are timed and delivered to be alternating pulses. One lower energy beam elicits its target to emit secondary electrons that are detected by an electron detector to produce an image. A second high-energy beam creates a virtual ground at its target. Voltage contrast images indicate whether there is continuity between the two conducting components.

摘要翻译： 描述用于检测连续性的基于电压对比度的装置，用于检测连续性的方法和系统用于评估诸如硅晶片的半导体芯片之类的微电路的导电部件。 两个光束被引导到样品上的两个分离的导电的，电浮动的部件，并被定时和传送成交替的脉冲。 一个较低的能量束引发其目标以发射由电子检测器检测以产生图像的二次电子。 第二个高能束在其目标上创建虚拟地面。 电压对比图像指示两个导电组件之间是否存在连续性。

公开(公告)号：US20070222470A1

公开(公告)日：2007-09-27

申请号：US11308407

申请日：2006-03-22

申请人： Oliver Patterson ,  Horatio Wildman

发明人： Oliver Patterson ,  Horatio Wildman

IPC分类号： G01R31/26

CPC分类号： G01R31/311 ,  G01R31/2632

摘要： Structure and methods of determining the complete location of a buried short using voltage contrast inspection are disclosed. In one embodiment, a method includes providing a test structure having a PN junction thereunder; and using the PN junction to determine the location of the buried short using voltage contrast (VC) inspection. A test structure may include a plurality of test elements each having a PN junction thereunder, wherein a location of the buried short within the test structure can be determined using the PN junction and the VC inspection. The PN junction forces a change in illumination brightness of a test element including the buried short, thus allowing determination of the complete location of a buried short.

摘要翻译： 公开了使用电压对比度检查来确定埋入短路的完整位置的结构和方法。 在一个实施例中，一种方法包括提供其下具有PN结的测试结构; 并使用PN结确定使用电压对比（VC）检测的埋入短路的位置。 测试结构可以包括多个测试元件，每个测试元件具有下面的PN结，其中可以使用PN结和VC检查来确定测试结构内的埋入短路的位置。 PN接头强制包括埋入短路的测试元件的照明亮度变化，从而允许确定埋入短路的完整位置。

公开(公告)号：US20070221990A1

公开(公告)日：2007-09-27

申请号：US11308408

申请日：2006-03-22

申请人： William Cote ,  Oliver Patterson

发明人： William Cote ,  Oliver Patterson

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L21/76264 ,  H01L21/84 ,  H01L27/1203

摘要： Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

摘要翻译： 公开了用于在绝缘体上硅（SOI）衬底上接地栅叠层和/或硅有源区前线结构的结构和方法，其可用作VC检验的测试结构。 在一个实施例中，结构包括其上具有SOI衬底的接地体硅衬底，SOI衬底包括绝缘体上硅（SOI）层和掩埋氧化物（BOX）层; 所述硅有源区在所述SOI层内具有至少一个指状元件，所述至少一个指状元件由浅沟槽隔离（STI）层隔离; 以及与所述至少一个指状元件相交并且穿过所述STI层和所述BOX层延伸到所述接地体硅衬底的多晶硅地，所述多晶硅接地与所述硅有源区和所述接地体硅衬底接触。

公开(公告)号：US20070229092A1

公开(公告)日：2007-10-04

申请号：US11308487

申请日：2006-03-29

申请人： Oliver Patterson ,  Huilong Zhu

发明人： Oliver Patterson ,  Huilong Zhu

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/307

摘要： Test structures and a method for voltage contrast (VC) inspection are disclosed. In one embodiment, the test structure includes: a gate stack that is grounded by a ground to maintain the gate stack in an off state during VC inspection, which allows NFET defect detection using VC inspection prior to contact dielectric deposition. The test structure may alternatively include a gate stack that is biased by a bias to maintain the gate stack in an on state during VC inspection. The method may detect source-to-drain shorts in a transistor using VC inspection by providing a gate stack over a source and drain region of the transistor that is grounded by a ground to maintain the gate stack in an off state during VC inspection; and inspecting the transistor using voltage contrast. If the drain of the NFET brightens during VC inspection, this indicates a source to drain short.

摘要翻译： 公开了用于电压对比（VC）检测的测试结构和方法。 在一个实施例中，测试结构包括：栅极堆叠，其通过接地来接地，以在VC检查期间将栅极堆叠保持在断开状态，这允许在接触介电沉积之前使用VC检查进行NFET缺陷检测。 测试结构可以替代地包括通过偏置偏置的栅极堆叠，以在VC检查期间将栅极堆叠保持在导通状态。 该方法可以通过在晶体管的源极和漏极区域上提供栅极堆叠来检测晶体管中的源极到漏极短路，所述栅极堆叠通过地线接地以在VC检查期间将栅极堆叠保持在断开状态; 并使用电压对比度检查晶体管。 如果在VC检查期间，NFET的漏极会亮起，这表明源极短路。